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Commit bf0df636 authored by Alan Cox's avatar Alan Cox Committed by Linus Torvalds
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8250_pci: Autodetect mainpine cards 



Add support for a whole range of boards. Some are partly autodetected but
not fully correctly others (PCI Express notably) not at all. Stick all
the right entries in.

Thanks to Mainpine for information and testing.

Signed-off-by: default avatarAlan Cox <alan@redhat.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 7201863c

drivers/serial/8250_pci.c

+120 −0
Original line number Diff line number Diff line
@@ -1036,6 +1036,7 @@ enum pci_board_num_t { 
	pbn_b0_2_115200,

	pbn_b0_4_115200,

	pbn_b0_5_115200,

	pbn_b0_8_115200,



	pbn_b0_1_921600,

	pbn_b0_2_921600,
@@ -1172,6 +1173,12 @@ static struct pciserial_board pci_boards[] __devinitdata = { 
		.base_baud	= 115200,

		.uart_offset	= 8,

	},

	[pbn_b0_8_115200] = {

		.flags		= FL_BASE0,

		.num_ports	= 8,

		.base_baud	= 115200,

		.uart_offset	= 8,

	},



	[pbn_b0_1_921600] = {

		.flags		= FL_BASE0,
@@ -2566,6 +2573,119 @@ static struct pci_device_id serial_pci_tbl[] = { 
	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,

		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,

		0, 0, pbn_b2_8_921600 },



	/*

	 * Mainpine series cards: Fairly standard layout but fools

	 * parts of the autodetect in some cases and uses otherwise

	 * unmatched communications subclasses in the PCI Express case

	 */



	{	/* RockForceDUO */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0200,

		0, 0, pbn_b0_2_115200 },

	{	/* RockForceQUATRO */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0300,

		0, 0, pbn_b0_4_115200 },

	{	/* RockForceDUO+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0400,

		0, 0, pbn_b0_2_115200 },

	{	/* RockForceQUATRO+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0500,

		0, 0, pbn_b0_4_115200 },

	{	/* RockForce+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0600,

		0, 0, pbn_b0_2_115200 },

	{	/* RockForce+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0700,

		0, 0, pbn_b0_4_115200 },

	{	/* RockForceOCTO+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0800,

		0, 0, pbn_b0_8_115200 },

	{	/* RockForceDUO+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0C00,

		0, 0, pbn_b0_2_115200 },

	{	/* RockForceQUARTRO+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x0D00,

		0, 0, pbn_b0_4_115200 },

	{	/* RockForceOCTO+ */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x1D00,

		0, 0, pbn_b0_8_115200 },

	{	/* RockForceD1 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2000,

		0, 0, pbn_b0_1_115200 },

	{	/* RockForceF1 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2100,

		0, 0, pbn_b0_1_115200 },

	{	/* RockForceD2 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2200,

		0, 0, pbn_b0_2_115200 },

	{	/* RockForceF2 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2300,

		0, 0, pbn_b0_2_115200 },

	{	/* RockForceD4 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2400,

		0, 0, pbn_b0_4_115200 },

	{	/* RockForceF4 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2500,

		0, 0, pbn_b0_4_115200 },

	{	/* RockForceD8 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2600,

		0, 0, pbn_b0_8_115200 },

	{	/* RockForceF8 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x2700,

		0, 0, pbn_b0_8_115200 },

	{	/* IQ Express D1 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3000,

		0, 0, pbn_b0_1_115200 },

	{	/* IQ Express F1 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3100,

		0, 0, pbn_b0_1_115200 },

	{	/* IQ Express D2 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3200,

		0, 0, pbn_b0_2_115200 },

	{	/* IQ Express F2 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3300,

		0, 0, pbn_b0_2_115200 },

	{	/* IQ Express D4 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3400,

		0, 0, pbn_b0_4_115200 },

	{	/* IQ Express F4 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3500,

		0, 0, pbn_b0_4_115200 },

	{	/* IQ Express D8 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3C00,

		0, 0, pbn_b0_8_115200 },

	{	/* IQ Express F8 */

		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,

		PCI_VENDOR_ID_MAINPINE, 0x3D00,

		0, 0, pbn_b0_8_115200 },





	/*

	 * PA Semi PA6T-1682M on-chip UART

	 */

include/linux/pci_ids.h

+2 −0
Original line number Diff line number Diff line
@@ -1995,6 +1995,8 @@ 
#define PCI_VENDOR_ID_TOPIC		0x151f

#define PCI_DEVICE_ID_TOPIC_TP560	0x0000



#define PCI_VENDOR_ID_MAINPINE		0x1522

#define PCI_DEVICE_ID_MAINPINE_PBRIDGE	0x0100

#define PCI_VENDOR_ID_ENE		0x1524

#define PCI_DEVICE_ID_ENE_CB712_SD	0x0550

#define PCI_DEVICE_ID_ENE_CB712_SD_2	0x0551