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Commit bbf1f8bf authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Initial pull request for radeon drm-next 3.13.  Highlights:
- Enable DPM on a number of asics by default
- Enable audio by default
- Dynamically power down dGPUs on PowerXpress systems
- Lots of bug fixes
* 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux: (36 commits)
  drm/radeon: don't share PPLLs on DCE4.1
  drm/radeon/dpm: fix typo in setting smc flag
  drm/radeon: fixup locking inversion between, mmap_sem and reservations
  drm/radeon: clear the page directory using the DMA
  drm/radeon: initially clear page tables
  drm/radeon: drop CP page table updates & cleanup v2
  drm/radeon: add vm_set_page tracepoint
  drm/radeon: rework and fix reset detection v2
  drm/radeon: don't use PACKET2 on CIK
  drm/radeon: fix UVD destroy IB size
  drm/radeon: activate UVD clocks before sending the destroy msg
  drm/radeon/si: fix define for MC_SEQ_TRAIN_WAKEUP_CNTL
  drm/radeon: fix endian handling in rlc buffer setup
  drm/radeon/dpm: retain user selected performance level across state changes
  drm/radeon: disable force performance state when thermal state is active
  drm/radeon: enable DPM by default on r7xx asics
  drm/radeon: enable DPM by default on evergreen asics
  drm/radeon: enable DPM by default on BTC asics
  drm/radeon: enable DPM by default on SI asics
  drm/radeon: enable DPM by default on SUMO/PALM APUs
  ...
parents 90c37067 70471860

drivers/gpu/drm/radeon/atombios_crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -1753,7 +1753,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
				if (pll != ATOM_PPLL_INVALID)

					return pll;

			}

		} else {

		} else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */

			/* use the same PPLL for all monitors with the same clock */

			pll = radeon_get_shared_nondp_ppll(crtc);

			if (pll != ATOM_PPLL_INVALID)

drivers/gpu/drm/radeon/atombios_encoders.c

+10 −14
Original line number Diff line number Diff line
@@ -1644,19 +1644,11 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);

			/* enable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);

		} else {

			/* setup and enable the encoder and transmitter */

			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

			/* some dce3.x boards have a bug in their transmitter control table.

			 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE

			 * does the same thing and more.

			 */

			if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&

			    (rdev->family != CHIP_RS880))

				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);

		}

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {

			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
@@ -1674,16 +1666,11 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
	case DRM_MODE_DPMS_STANDBY:

	case DRM_MODE_DPMS_SUSPEND:

	case DRM_MODE_DPMS_OFF:

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

		} else if (ASIC_IS_DCE4(rdev)) {

		if (ASIC_IS_DCE4(rdev)) {

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

		} else {

			/* disable the encoder and transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);

		}
@@ -2392,6 +2379,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 


	/* this is needed for the pll/ss setup to work correctly in some cases */

	atombios_set_encoder_crtc_source(encoder);

	/* set up the FMT blocks */

	if (ASIC_IS_DCE8(rdev))

		dce8_program_fmt(encoder);

	else if (ASIC_IS_DCE4(rdev))

		dce4_program_fmt(encoder);

	else if (ASIC_IS_DCE3(rdev))

		dce3_program_fmt(encoder);

	else if (ASIC_IS_AVIVO(rdev))

		avivo_program_fmt(encoder);

}



static void radeon_atom_encoder_commit(struct drm_encoder *encoder)

drivers/gpu/drm/radeon/cik.c

+168 −85
Original line number Diff line number Diff line
@@ -67,11 +67,6 @@ extern void si_init_uvd_internal_cg(struct radeon_device *rdev); 
extern int cik_sdma_resume(struct radeon_device *rdev);

extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);

extern void cik_sdma_fini(struct radeon_device *rdev);

extern void cik_sdma_vm_set_page(struct radeon_device *rdev,

				 struct radeon_ib *ib,

				 uint64_t pe,

				 uint64_t addr, unsigned count,

				 uint32_t incr, uint32_t flags);

static void cik_rlc_stop(struct radeon_device *rdev);

static void cik_pcie_gen3_enable(struct radeon_device *rdev);

static void cik_program_aspm(struct radeon_device *rdev);
@@ -3094,6 +3089,85 @@ void cik_semaphore_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);

}



/**

 * cik_copy_cpdma - copy pages using the CP DMA engine

 *

 * @rdev: radeon_device pointer

 * @src_offset: src GPU address

 * @dst_offset: dst GPU address

 * @num_gpu_pages: number of GPU pages to xfer

 * @fence: radeon fence object

 *

 * Copy GPU paging using the CP DMA engine (CIK+).

 * Used by the radeon ttm implementation to move pages if

 * registered as the asic copy callback.

 */

int cik_copy_cpdma(struct radeon_device *rdev,

		   uint64_t src_offset, uint64_t dst_offset,

		   unsigned num_gpu_pages,

		   struct radeon_fence **fence)

{

	struct radeon_semaphore *sem = NULL;

	int ring_index = rdev->asic->copy.blit_ring_index;

	struct radeon_ring *ring = &rdev->ring[ring_index];

	u32 size_in_bytes, cur_size_in_bytes, control;

	int i, num_loops;

	int r = 0;



	r = radeon_semaphore_create(rdev, &sem);

	if (r) {

		DRM_ERROR("radeon: moving bo (%d).\n", r);

		return r;

	}



	size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);

	num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);

	r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);

	if (r) {

		DRM_ERROR("radeon: moving bo (%d).\n", r);

		radeon_semaphore_free(rdev, &sem, NULL);

		return r;

	}



	if (radeon_fence_need_sync(*fence, ring->idx)) {

		radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,

					    ring->idx);

		radeon_fence_note_sync(*fence, ring->idx);

	} else {

		radeon_semaphore_free(rdev, &sem, NULL);

	}



	for (i = 0; i < num_loops; i++) {

		cur_size_in_bytes = size_in_bytes;

		if (cur_size_in_bytes > 0x1fffff)

			cur_size_in_bytes = 0x1fffff;

		size_in_bytes -= cur_size_in_bytes;

		control = 0;

		if (size_in_bytes == 0)

			control |= PACKET3_DMA_DATA_CP_SYNC;

		radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));

		radeon_ring_write(ring, control);

		radeon_ring_write(ring, lower_32_bits(src_offset));

		radeon_ring_write(ring, upper_32_bits(src_offset));

		radeon_ring_write(ring, lower_32_bits(dst_offset));

		radeon_ring_write(ring, upper_32_bits(dst_offset));

		radeon_ring_write(ring, cur_size_in_bytes);

		src_offset += cur_size_in_bytes;

		dst_offset += cur_size_in_bytes;

	}



	r = radeon_fence_emit(rdev, fence, ring->idx);

	if (r) {

		radeon_ring_unlock_undo(rdev, ring);

		return r;

	}



	radeon_ring_unlock_commit(rdev, ring);

	radeon_semaphore_free(rdev, &sem, *fence);



	return r;

}



/*

 * IB stuff

 */
@@ -4824,62 +4898,6 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 
	}

}



/**

 * cik_vm_set_page - update the page tables using sDMA

 *

 * @rdev: radeon_device pointer

 * @ib: indirect buffer to fill with commands

 * @pe: addr of the page entry

 * @addr: dst addr to write into pe

 * @count: number of page entries to update

 * @incr: increase next addr by incr bytes

 * @flags: access flags

 *

 * Update the page tables using CP or sDMA (CIK).

 */

void cik_vm_set_page(struct radeon_device *rdev,

		     struct radeon_ib *ib,

		     uint64_t pe,

		     uint64_t addr, unsigned count,

		     uint32_t incr, uint32_t flags)

{

	uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);

	uint64_t value;

	unsigned ndw;



	if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {

		/* CP */

		while (count) {

			ndw = 2 + count * 2;

			if (ndw > 0x3FFE)

				ndw = 0x3FFE;



			ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);

			ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |

						    WRITE_DATA_DST_SEL(1));

			ib->ptr[ib->length_dw++] = pe;

			ib->ptr[ib->length_dw++] = upper_32_bits(pe);

			for (; ndw > 2; ndw -= 2, --count, pe += 8) {

				if (flags & RADEON_VM_PAGE_SYSTEM) {

					value = radeon_vm_map_gart(rdev, addr);

					value &= 0xFFFFFFFFFFFFF000ULL;

				} else if (flags & RADEON_VM_PAGE_VALID) {

					value = addr;

				} else {

					value = 0;

				}

				addr += incr;

				value |= r600_flags;

				ib->ptr[ib->length_dw++] = value;

				ib->ptr[ib->length_dw++] = upper_32_bits(value);

			}

		}

	} else {

		/* DMA */

		cik_sdma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);

	}

}



/*

 * RLC

 * The RLC is a multi-purpose microengine that handles a
@@ -5546,7 +5564,7 @@ void cik_init_cp_pg_table(struct radeon_device *rdev) 
		}



		for (i = 0; i < CP_ME_TABLE_SIZE; i ++) {

			dst_ptr[bo_offset + i] = be32_to_cpu(fw_data[table_offset + i]);

			dst_ptr[bo_offset + i] = cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));

		}

		bo_offset += CP_ME_TABLE_SIZE;

	}
@@ -5768,52 +5786,53 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer) 
	if (buffer == NULL)

		return;



	buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);

	buffer[count++] = PACKET3_PREAMBLE_BEGIN_CLEAR_STATE;

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);



	buffer[count++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1);

	buffer[count++] = 0x80000000;

	buffer[count++] = 0x80000000;

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));

	buffer[count++] = cpu_to_le32(0x80000000);

	buffer[count++] = cpu_to_le32(0x80000000);



	for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {

		for (ext = sect->section; ext->extent != NULL; ++ext) {

			if (sect->id == SECT_CONTEXT) {

				buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count);

				buffer[count++] = ext->reg_index - 0xa000;

				buffer[count++] =

					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

				buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);

				for (i = 0; i < ext->reg_count; i++)

					buffer[count++] = ext->extent[i];

					buffer[count++] = cpu_to_le32(ext->extent[i]);

			} else {

				return;

			}

		}

	}



	buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);

	buffer[count++] = PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START;

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));

	buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

	switch (rdev->family) {

	case CHIP_BONAIRE:

		buffer[count++] = 0x16000012;

		buffer[count++] = 0x00000000;

		buffer[count++] = cpu_to_le32(0x16000012);

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	case CHIP_KAVERI:

		buffer[count++] = 0x00000000; /* XXX */

		buffer[count++] = 0x00000000;

		buffer[count++] = cpu_to_le32(0x00000000); /* XXX */

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	case CHIP_KABINI:

		buffer[count++] = 0x00000000; /* XXX */

		buffer[count++] = 0x00000000;

		buffer[count++] = cpu_to_le32(0x00000000); /* XXX */

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	default:

		buffer[count++] = 0x00000000;

		buffer[count++] = 0x00000000;

		buffer[count++] = cpu_to_le32(0x00000000);

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	}



	buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);

	buffer[count++] = PACKET3_PREAMBLE_END_CLEAR_STATE;

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);



	buffer[count++] = PACKET3(PACKET3_CLEAR_STATE, 0);

	buffer[count++] = 0;

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));

	buffer[count++] = cpu_to_le32(0);

}



static void cik_init_pg(struct radeon_device *rdev)
@@ -7108,7 +7127,7 @@ static int cik_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     CP_RB0_RPTR, CP_RB0_WPTR,

			     RADEON_CP_PACKET2);

			     PACKET3(PACKET3_NOP, 0x3FFF));

	if (r)

		return r;
@@ -7418,6 +7437,70 @@ void cik_fini(struct radeon_device *rdev) 
	rdev->bios = NULL;

}



void dce8_program_fmt(struct drm_encoder *encoder)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	int bpc = 0;

	u32 tmp = 0;

	enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;



	if (connector) {

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);

		bpc = radeon_get_monitor_bpc(connector);

		dither = radeon_connector->dither;

	}



	/* LVDS/eDP FMT is set up by atom */

	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)

		return;



	/* not needed for analog */

	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||

	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))

		return;



	if (bpc == 0)

		return;



	switch (bpc) {

	case 6:

		if (dither == RADEON_FMT_DITHER_ENABLE)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));

		break;

	case 8:

		if (dither == RADEON_FMT_DITHER_ENABLE)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_RGB_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));

		break;

	case 10:

		if (dither == RADEON_FMT_DITHER_ENABLE)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_RGB_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));

		break;

	default:

		/* not needed */

		break;

	}



	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

}



/* display watermark setup */

/**

 * dce8_line_buffer_adjust - Set up the line buffer

drivers/gpu/drm/radeon/cik_sdma.c

+9 −13
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <drm/drmP.h>

#include "radeon.h"

#include "radeon_asic.h"

#include "radeon_trace.h"

#include "cikd.h"



/* sdma */
@@ -653,11 +654,12 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, 
			  uint64_t addr, unsigned count,

			  uint32_t incr, uint32_t flags)

{

	uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);

	uint64_t value;

	unsigned ndw;



	if (flags & RADEON_VM_PAGE_SYSTEM) {

	trace_radeon_vm_set_page(pe, addr, count, incr, flags);



	if (flags & R600_PTE_SYSTEM) {

		while (count) {

			ndw = count * 2;

			if (ndw > 0xFFFFE)
@@ -669,16 +671,10 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, 
			ib->ptr[ib->length_dw++] = upper_32_bits(pe);

			ib->ptr[ib->length_dw++] = ndw;

			for (; ndw > 0; ndw -= 2, --count, pe += 8) {

				if (flags & RADEON_VM_PAGE_SYSTEM) {

				value = radeon_vm_map_gart(rdev, addr);

				value &= 0xFFFFFFFFFFFFF000ULL;

				} else if (flags & RADEON_VM_PAGE_VALID) {

					value = addr;

				} else {

					value = 0;

				}

				addr += incr;

				value |= r600_flags;

				value |= flags;

				ib->ptr[ib->length_dw++] = value;

				ib->ptr[ib->length_dw++] = upper_32_bits(value);

			}
@@ -689,7 +685,7 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, 
			if (ndw > 0x7FFFF)

				ndw = 0x7FFFF;



			if (flags & RADEON_VM_PAGE_VALID)

			if (flags & R600_PTE_VALID)

				value = addr;

			else

				value = 0;
@@ -697,7 +693,7 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, 
			ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);

			ib->ptr[ib->length_dw++] = pe; /* dst addr */

			ib->ptr[ib->length_dw++] = upper_32_bits(pe);

			ib->ptr[ib->length_dw++] = r600_flags; /* mask */

			ib->ptr[ib->length_dw++] = flags; /* mask */

			ib->ptr[ib->length_dw++] = 0;

			ib->ptr[ib->length_dw++] = value; /* value */

			ib->ptr[ib->length_dw++] = upper_32_bits(value);

drivers/gpu/drm/radeon/cikd.h

+95 −0
Original line number Diff line number Diff line
@@ -906,6 +906,39 @@ 
#define DPG_PIPE_STUTTER_CONTROL                          0x6cd4

#       define STUTTER_ENABLE                             (1 << 0)



/* DCE8 FMT blocks */

#define FMT_DYNAMIC_EXP_CNTL                 0x6fb4

#       define FMT_DYNAMIC_EXP_EN            (1 << 0)

#       define FMT_DYNAMIC_EXP_MODE          (1 << 4)

        /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */

#define FMT_CONTROL                          0x6fb8

#       define FMT_PIXEL_ENCODING            (1 << 16)

        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */

#define FMT_BIT_DEPTH_CONTROL                0x6fc8

#       define FMT_TRUNCATE_EN               (1 << 0)

#       define FMT_TRUNCATE_MODE             (1 << 1)

#       define FMT_TRUNCATE_DEPTH(x)         ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

#       define FMT_SPATIAL_DITHER_EN         (1 << 8)

#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)

#       define FMT_SPATIAL_DITHER_DEPTH(x)   ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)

#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)

#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)

#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)

#       define FMT_TEMPORAL_DITHER_DEPTH(x)  ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)

#       define FMT_TEMPORAL_LEVEL            (1 << 24)

#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)

#       define FMT_25FRC_SEL(x)              ((x) << 26)

#       define FMT_50FRC_SEL(x)              ((x) << 28)

#       define FMT_75FRC_SEL(x)              ((x) << 30)

#define FMT_CLAMP_CONTROL                    0x6fe4

#       define FMT_CLAMP_DATA_EN             (1 << 0)

#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)

#       define FMT_CLAMP_6BPC                0

#       define FMT_CLAMP_8BPC                1

#       define FMT_CLAMP_10BPC               2



#define	GRBM_CNTL					0x8000

#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
@@ -1714,6 +1747,68 @@ 
#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)

#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)

#define	PACKET3_DMA_DATA				0x50

/* 1. header

 * 2. CONTROL

 * 3. SRC_ADDR_LO or DATA [31:0]

 * 4. SRC_ADDR_HI [31:0]

 * 5. DST_ADDR_LO [31:0]

 * 6. DST_ADDR_HI [7:0]

 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]

 */

/* CONTROL */

#              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)

                /* 0 - ME

		 * 1 - PFP

		 */

#              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)

                /* 0 - LRU

		 * 1 - Stream

		 * 2 - Bypass

		 */

#              define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)

#              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)

                /* 0 - DST_ADDR using DAS

		 * 1 - GDS

		 * 3 - DST_ADDR using L2

		 */

#              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)

                /* 0 - LRU

		 * 1 - Stream

		 * 2 - Bypass

		 */

#              define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)

#              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)

                /* 0 - SRC_ADDR using SAS

		 * 1 - GDS

		 * 2 - DATA

		 * 3 - SRC_ADDR using L2

		 */

#              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)

/* COMMAND */

#              define PACKET3_DMA_DATA_DIS_WC      (1 << 21)

#              define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)

#              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)

#              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)

#define	PACKET3_AQUIRE_MEM				0x58

#define	PACKET3_REWIND					0x59

#define	PACKET3_LOAD_UCONFIG_REG			0x5E