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Commit babed555 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.c 



Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: default avatarTomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b5e00af8

arch/mips/include/asm/ptrace.h

+4 −0
Original line number Diff line number Diff line
@@ -48,6 +48,10 @@ struct pt_regs { 
#ifdef CONFIG_MIPS_MT_SMTC

	unsigned long cp0_tcstatus;

#endif /* CONFIG_MIPS_MT_SMTC */

#ifdef CONFIG_CPU_CAVIUM_OCTEON

	unsigned long long mpl[3];        /* MTM{0,1,2} */

	unsigned long long mtp[3];        /* MTP{0,1,2} */

#endif

} __attribute__ ((aligned (8)));



/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */

arch/mips/kernel/asm-offsets.c

+31 −0
Original line number Diff line number Diff line
@@ -64,6 +64,10 @@ void output_ptreg_defines(void) 
#ifdef CONFIG_MIPS_MT_SMTC

	OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);

#endif /* CONFIG_MIPS_MT_SMTC */

#ifdef CONFIG_CPU_CAVIUM_OCTEON

	OFFSET(PT_MPL, pt_regs, mpl);

	OFFSET(PT_MTP, pt_regs, mtp);

#endif /* CONFIG_CPU_CAVIUM_OCTEON */

	DEFINE(PT_SIZE, sizeof(struct pt_regs));

	BLANK();

}
@@ -295,3 +299,30 @@ void output_irq_cpustat_t_defines(void) 
	DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t));

	BLANK();

}



#ifdef CONFIG_CPU_CAVIUM_OCTEON

void output_octeon_cop2_state_defines(void)

{

	COMMENT("Octeon specific octeon_cop2_state offsets.");

	OFFSET(OCTEON_CP2_CRC_IV,	octeon_cop2_state, cop2_crc_iv);

	OFFSET(OCTEON_CP2_CRC_LENGTH,	octeon_cop2_state, cop2_crc_length);

	OFFSET(OCTEON_CP2_CRC_POLY,	octeon_cop2_state, cop2_crc_poly);

	OFFSET(OCTEON_CP2_LLM_DAT,	octeon_cop2_state, cop2_llm_dat);

	OFFSET(OCTEON_CP2_3DES_IV,	octeon_cop2_state, cop2_3des_iv);

	OFFSET(OCTEON_CP2_3DES_KEY,	octeon_cop2_state, cop2_3des_key);

	OFFSET(OCTEON_CP2_3DES_RESULT,	octeon_cop2_state, cop2_3des_result);

	OFFSET(OCTEON_CP2_AES_INP0,	octeon_cop2_state, cop2_aes_inp0);

	OFFSET(OCTEON_CP2_AES_IV,	octeon_cop2_state, cop2_aes_iv);

	OFFSET(OCTEON_CP2_AES_KEY,	octeon_cop2_state, cop2_aes_key);

	OFFSET(OCTEON_CP2_AES_KEYLEN,	octeon_cop2_state, cop2_aes_keylen);

	OFFSET(OCTEON_CP2_AES_RESULT,	octeon_cop2_state, cop2_aes_result);

	OFFSET(OCTEON_CP2_GFM_MULT,	octeon_cop2_state, cop2_gfm_mult);

	OFFSET(OCTEON_CP2_GFM_POLY,	octeon_cop2_state, cop2_gfm_poly);

	OFFSET(OCTEON_CP2_GFM_RESULT,	octeon_cop2_state, cop2_gfm_result);

	OFFSET(OCTEON_CP2_HSH_DATW,	octeon_cop2_state, cop2_hsh_datw);

	OFFSET(OCTEON_CP2_HSH_IVW,	octeon_cop2_state, cop2_hsh_ivw);

	OFFSET(THREAD_CP2,	task_struct, thread.cp2);

	OFFSET(THREAD_CVMSEG,	task_struct, thread.cvmseg.cvmseg);

	BLANK();

}

#endif