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Commit a855039e authored by Kukjin Kim's avatar Kukjin Kim
Browse files

ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock 



This patch changes prefix of the clk register from S5P_ to
EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix
exynos4_ on clk declarations.

Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent b1d6c5b2

arch/arm/mach-exynos/clock-exynos4.c

+514 −514

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-exynos/clock-exynos4.h

+7 −8
Original line number Original line Diff line number Diff line 
/*

/*

 *

 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *		http://www.samsung.com

 *

 *

 * Header file for exynos4 clock support

 * Header file for exynos4 clock support
@@ -15,14 +14,14 @@ 




#include <linux/clk.h>

#include <linux/clk.h>





extern struct clksrc_clk clk_mout_mpll;

extern struct clksrc_clk exynos4_clk_aclk_133;

extern struct clksrc_clk clk_aclk_133;

extern struct clksrc_clk exynos4_clk_mout_mpll;





extern struct clksrc_sources clkset_mout_corebus;

extern struct clksrc_sources exynos4_clkset_mout_corebus;

extern struct clksrc_sources clkset_group;

extern struct clksrc_sources exynos4_clkset_group;





extern struct clk *clkset_aclk_top_list[];

extern struct clk *exynos4_clkset_aclk_top_list[];

extern struct clk *clkset_group_list[];

extern struct clk *exynos4_clkset_group_list[];





extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);

arch/arm/mach-exynos/clock-exynos4210.c

+21 −23
Original line number Original line Diff line number Diff line 
/*

/*

 * linux/arch/arm/mach-exynos4/clock-exynos4210.c

 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *		http://www.samsung.com

 *

 *

 * EXYNOS4210 - Clock support

 * EXYNOS4210 - Clock support
@@ -34,14 +32,14 @@ 




#ifdef CONFIG_PM_SLEEP

#ifdef CONFIG_PM_SLEEP

static struct sleep_save exynos4210_clock_save[] = {

static struct sleep_save exynos4210_clock_save[] = {

	SAVE_ITEM(S5P_CLKSRC_IMAGE),

	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),

	SAVE_ITEM(S5P_CLKSRC_LCD1),

	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),

	SAVE_ITEM(S5P_CLKDIV_IMAGE),

	SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),

	SAVE_ITEM(S5P_CLKDIV_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),

	SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),

	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),

	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),

	SAVE_ITEM(S5P_CLKGATE_IP_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),

	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),

	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),

};

};

#endif

#endif
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = { 




static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)

static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)

{

{

	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);

	return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);

}

}





static struct clksrc_clk clksrcs[] = {

static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = { 
			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 24),

			.ctrlbit	= (1 << 24),

		},

		},

		.sources = &clkset_mout_corebus,

		.sources = &exynos4_clkset_mout_corebus,

		.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },

		.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },

		.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },

	}, {

	}, {

		.clk		= {

		.clk		= {

			.name		= "sclk_fimd",

			.name		= "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = { 
			.enable		= exynos4_clksrc_mask_lcd1_ctrl,

			.enable		= exynos4_clksrc_mask_lcd1_ctrl,

			.ctrlbit	= (1 << 0),

			.ctrlbit	= (1 << 0),

		},

		},

		.sources = &clkset_group,

		.sources = &exynos4_clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },

	},

	},

};

};
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = { 
	{

	{

		.name		= "sataphy",

		.name		= "sataphy",

		.id		= -1,

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 3),

		.ctrlbit	= (1 << 3),

	}, {

	}, {

		.name		= "sata",

		.name		= "sata",

		.id		= -1,

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 10),

		.ctrlbit	= (1 << 10),

	}, {

	}, {
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void) 
{

{

	int ptr;

	int ptr;





	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;

	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;

	clk_mout_mpll.reg_src.shift = 8;

	exynos4_clk_mout_mpll.reg_src.shift = 8;

	clk_mout_mpll.reg_src.size = 1;

	exynos4_clk_mout_mpll.reg_src.size = 1;





	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);

		s3c_register_clksrc(sysclks[ptr], 1);

arch/arm/mach-exynos/clock-exynos4212.c

+13 −15
Original line number Original line Diff line number Diff line 
/*

/*

 * linux/arch/arm/mach-exynos4/clock-exynos4212.c

 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *		http://www.samsung.com

 *

 *

 * EXYNOS4212 - Clock support

 * EXYNOS4212 - Clock support
@@ -34,16 +32,16 @@ 




#ifdef CONFIG_PM_SLEEP

#ifdef CONFIG_PM_SLEEP

static struct sleep_save exynos4212_clock_save[] = {

static struct sleep_save exynos4212_clock_save[] = {

	SAVE_ITEM(S5P_CLKSRC_IMAGE),

	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),

	SAVE_ITEM(S5P_CLKDIV_IMAGE),

	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),

	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),

	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),

	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),

	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),

};

};

#endif

#endif





static struct clk *clk_src_mpll_user_list[] = {

static struct clk *clk_src_mpll_user_list[] = {

	[0] = &clk_fin_mpll,

	[0] = &clk_fin_mpll,

	[1] = &clk_mout_mpll.clk,

	[1] = &exynos4_clk_mout_mpll.clk,

};

};





static struct clksrc_sources clk_src_mpll_user = {

static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = { 
		.name		= "mout_mpll_user",

		.name		= "mout_mpll_user",

	},

	},

	.sources	= &clk_src_mpll_user,

	.sources	= &clk_src_mpll_user,

	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },

	.reg_src	= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },

};

};





static struct clksrc_clk *sysclks[] = {

static struct clksrc_clk *sysclks[] = {
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void) 
	int ptr;

	int ptr;





	/* usbphy1 is removed */

	/* usbphy1 is removed */

	clkset_group_list[4] = NULL;

	exynos4_clkset_group_list[4] = NULL;





	/* mout_mpll_user is used */

	/* mout_mpll_user is used */

	clkset_group_list[6] = &clk_mout_mpll_user.clk;

	exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;

	clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;

	exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;





	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;

	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;

	clk_mout_mpll.reg_src.shift = 12;

	exynos4_clk_mout_mpll.reg_src.shift = 12;

	clk_mout_mpll.reg_src.size = 1;

	exynos4_clk_mout_mpll.reg_src.size = 1;





	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);

		s3c_register_clksrc(sysclks[ptr], 1);

arch/arm/mach-exynos/common.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -15,12 +15,21 @@ 
void exynos_init_io(struct map_desc *mach_desc, int size);

void exynos_init_io(struct map_desc *mach_desc, int size);

void exynos4_init_irq(void);

void exynos4_init_irq(void);





#ifdef CONFIG_ARCH_EXYNOS4

void exynos4_register_clocks(void);

void exynos4_register_clocks(void);

void exynos4_setup_clocks(void);

void exynos4_setup_clocks(void);





void exynos4210_register_clocks(void);

void exynos4210_register_clocks(void);

void exynos4212_register_clocks(void);

void exynos4212_register_clocks(void);





#else

#define exynos4_register_clocks()

#define exynos4_setup_clocks()



#define exynos4210_register_clocks()

#define exynos4212_register_clocks()

#endif



void exynos4_restart(char mode, const char *cmd);

void exynos4_restart(char mode, const char *cmd);





extern struct sys_timer exynos4_timer;

extern struct sys_timer exynos4_timer;