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Commit a7ce8edc authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 3026/1: S3C2410 - avoid possible overflow in pll calculations 



Patch from Ben Dooks

Avoid the possiblity that if the board is using
a 16.9334 or higher crystal with a high PLL
multiplier, then the pll value could overflow
the capability of an int.

Also fix the value types of the intermediate
variables to unsigned int.

Rewrite of patch from Guillaume Gourat

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b2640b42

include/asm-arm/arch-s3c2410/regs-clock.h

+11 −4
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
 *    10-Feb-2005 Ben Dooks	    Fixed CAMDIVN address (Guillaume Gourat)

 *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA

 *    27-Aug-2005 Ben Dooks	    Add clock-slow info

 *    20-Oct-2005 Ben Dooks	    Fixed overflow in PLL (Guillaume Gourat)

*/



#ifndef __ASM_ARM_REGS_CLOCK
@@ -83,10 +84,13 @@ 


#ifndef __ASSEMBLY__



#include <asm/div64.h>



static inline unsigned int

s3c2410_get_pll(int pllval, int baseclk)

s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)

{

	int mdiv, pdiv, sdiv;

	unsigned int mdiv, pdiv, sdiv;

	uint64_t fvco;



	mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;

	pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +100,10 @@ s3c2410_get_pll(int pllval, int baseclk) 
	pdiv &= S3C2410_PLLCON_PDIVMASK;

	sdiv &= S3C2410_PLLCON_SDIVMASK;



	return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);

	fvco = (uint64_t)baseclk * (mdiv + 8);

	do_div(fvco, (pdiv + 2) << sdiv);



	return (unsigned int)fvco;

}



#endif /* __ASSEMBLY__ */