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Commit a0fd065c authored by Dmitry Kravkov's avatar Dmitry Kravkov Committed by David S. Miller
Browse files

bnx2x: fix possible deadlock in HC hw block 



The possible deadlock (on 57710 devices only) will prevent from the
device to generate interrupts.

Signed-off-by: default avatarDmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8723e1b4

drivers/net/bnx2x/bnx2x_main.c

+29 −8
Original line number Diff line number Diff line
@@ -1111,6 +1111,7 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp) 
			HC_CONFIG_0_REG_INT_LINE_EN_0 |

			HC_CONFIG_0_REG_ATTN_BIT_EN_0);



		if (!CHIP_IS_E1(bp)) {

			DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",

			   val, port, addr);
@@ -1118,6 +1119,10 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp) 


			val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;

		}

	}



	if (CHIP_IS_E1(bp))

		REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);



	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",

	   val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
@@ -1212,6 +1217,22 @@ static void bnx2x_hc_int_disable(struct bnx2x *bp) 
	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;

	u32 val = REG_RD(bp, addr);



	/*

	 * in E1 we must use only PCI configuration space to disable

	 * MSI/MSIX capablility

	 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block

	 */

	if (CHIP_IS_E1(bp)) {

		/*  Since IGU_PF_CONF_MSI_MSIX_EN still always on

		 *  Use mask register to prevent from HC sending interrupts

		 *  after we exit the function

		 */

		REG_WR(bp, HC_REG_INT_MASK + port*4, 0);



		val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |

			 HC_CONFIG_0_REG_INT_LINE_EN_0 |

			 HC_CONFIG_0_REG_ATTN_BIT_EN_0);

	} else

		val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |

			 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |

			 HC_CONFIG_0_REG_INT_LINE_EN_0 |