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Commit 9f271369 authored by Sachin Kamat's avatar Sachin Kamat Committed by Mike Turquette
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clk: exynos4: Add clock entries for TMU 



Added clock entries for thermal management unit (TMU) for
Exynos4 SoCs.

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent b38a5040

Documentation/devicetree/bindings/clock/exynos4-clock.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable. 
  spi0_isp_sclk       380     Exynos4x12

  spi0_isp_sclk       380     Exynos4x12

  spi1_isp_sclk       381     Exynos4x12

  spi1_isp_sclk       381     Exynos4x12

  uart_isp_sclk       382     Exynos4x12

  uart_isp_sclk       382     Exynos4x12

  tmu_apbif           383





		[Mux Clocks]

		[Mux Clocks]

drivers/clk/samsung/clk-exynos4.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -169,7 +169,7 @@ enum exynos4_clks { 
	gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,

	gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,

	mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,

	mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,

	asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,

	asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,

	spi1_isp_sclk, uart_isp_sclk,

	spi1_isp_sclk, uart_isp_sclk, tmu_apbif,





	/* mux clocks */

	/* mux clocks */

	mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,

	mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
@@ -814,6 +814,7 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 
	GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),

	GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),

	GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",

	GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",

			E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),

			E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),

	GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0),

};

};





/* list of gate clocks supported in exynos4x12 soc */

/* list of gate clocks supported in exynos4x12 soc */
@@ -915,6 +916,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
	GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,

	GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,

			CLK_IGNORE_UNUSED, 0),

			CLK_IGNORE_UNUSED, 0),

	GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),

	GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),

	GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0),

};

};





/*

/*