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Commit 9ce079e4 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Prepare to consolidate fence writing 



Update the existing architecture specific fence writing routines to
either update the fence to point to a tiled object or to clear them in
preparation to remove the other fence writing routes.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 18991845

drivers/gpu/drm/i915/i915_gem.c

+108 −103
Original line number Diff line number Diff line
@@ -2163,14 +2163,15 @@ int i915_gpu_idle(struct drm_device *dev, bool do_retire) 
	return 0;

}



static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj)

static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,

					struct drm_i915_gem_object *obj)

{

	struct drm_device *dev = obj->base.dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 size = obj->gtt_space->size;

	int regnum = obj->fence_reg;

	uint64_t val;



	if (obj) {

		u32 size = obj->gtt_space->size;



		val = (uint64_t)((obj->gtt_offset + size - 4096) &

				 0xfffff000) << 32;

		val |= obj->gtt_offset & 0xfffff000;
@@ -2180,20 +2181,22 @@ static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj) 
		if (obj->tiling_mode == I915_TILING_Y)

			val |= 1 << I965_FENCE_TILING_Y_SHIFT;

		val |= I965_FENCE_REG_VALID;

	} else

		val = 0;



	I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);



	return 0;

	I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);

	POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);

}



static int i965_write_fence_reg(struct drm_i915_gem_object *obj)

static void i965_write_fence_reg(struct drm_device *dev, int reg,

				 struct drm_i915_gem_object *obj)

{

	struct drm_device *dev = obj->base.dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 size = obj->gtt_space->size;

	int regnum = obj->fence_reg;

	uint64_t val;



	if (obj) {

		u32 size = obj->gtt_space->size;



		val = (uint64_t)((obj->gtt_offset + size - 4096) &

				 0xfffff000) << 32;

		val |= obj->gtt_offset & 0xfffff000;
@@ -2201,26 +2204,29 @@ static int i965_write_fence_reg(struct drm_i915_gem_object *obj) 
		if (obj->tiling_mode == I915_TILING_Y)

			val |= 1 << I965_FENCE_TILING_Y_SHIFT;

		val |= I965_FENCE_REG_VALID;

	} else

		val = 0;



	I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);



	return 0;

	I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);

	POSTING_READ(FENCE_REG_965_0 + reg * 8);

}



static int i915_write_fence_reg(struct drm_i915_gem_object *obj)

static void i915_write_fence_reg(struct drm_device *dev, int reg,

				 struct drm_i915_gem_object *obj)

{

	struct drm_device *dev = obj->base.dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 val;



	if (obj) {

		u32 size = obj->gtt_space->size;

	u32 fence_reg, val, pitch_val;

		int pitch_val;

		int tile_width;



	if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||

		WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||

		     (size & -size) != size ||

		     (obj->gtt_offset & (size - 1)),

		     "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",

		 obj->gtt_offset, obj->map_and_fenceable, size))

		return -EINVAL;

		     obj->gtt_offset, obj->map_and_fenceable, size);



		if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))

			tile_width = 128;
@@ -2237,33 +2243,33 @@ static int i915_write_fence_reg(struct drm_i915_gem_object *obj) 
		val |= I915_FENCE_SIZE_BITS(size);

		val |= pitch_val << I830_FENCE_PITCH_SHIFT;

		val |= I830_FENCE_REG_VALID;

	} else

		val = 0;



	fence_reg = obj->fence_reg;

	if (fence_reg < 8)

		fence_reg = FENCE_REG_830_0 + fence_reg * 4;

	if (reg < 8)

		reg = FENCE_REG_830_0 + reg * 4;

	else

		fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;

		reg = FENCE_REG_945_8 + (reg - 8) * 4;



	I915_WRITE(fence_reg, val);



	return 0;

	I915_WRITE(reg, val);

	POSTING_READ(reg);

}



static int i830_write_fence_reg(struct drm_i915_gem_object *obj)

static void i830_write_fence_reg(struct drm_device *dev, int reg,

				struct drm_i915_gem_object *obj)

{

	struct drm_device *dev = obj->base.dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 size = obj->gtt_space->size;

	int regnum = obj->fence_reg;

	uint32_t val;



	if (obj) {

		u32 size = obj->gtt_space->size;

		uint32_t pitch_val;



	if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||

		WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||

		     (size & -size) != size ||

		     (obj->gtt_offset & (size - 1)),

		     "object 0x%08x not 512K or pot-size 0x%08x aligned\n",

		 obj->gtt_offset, size))

		return -EINVAL;

		     obj->gtt_offset, size);



		pitch_val = obj->stride / 128;

		pitch_val = ffs(pitch_val) - 1;
@@ -2274,10 +2280,25 @@ static int i830_write_fence_reg(struct drm_i915_gem_object *obj) 
		val |= I830_FENCE_SIZE_BITS(size);

		val |= pitch_val << I830_FENCE_PITCH_SHIFT;

		val |= I830_FENCE_REG_VALID;

	} else

		val = 0;



	I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);

	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);

	POSTING_READ(FENCE_REG_830_0 + reg * 4);

}



	return 0;

static void i915_gem_write_fence(struct drm_device *dev, int reg,

				 struct drm_i915_gem_object *obj)

{

	switch (INTEL_INFO(dev)->gen) {

	case 7:

	case 6: sandybridge_write_fence_reg(dev, reg, obj); break;

	case 5:

	case 4: i965_write_fence_reg(dev, reg, obj); break;

	case 3: i915_write_fence_reg(dev, reg, obj); break;

	case 2: i830_write_fence_reg(dev, reg, obj); break;

	default: break;

	}

}



static int
@@ -2447,24 +2468,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj) 


update:

	obj->tiling_changed = false;

	switch (INTEL_INFO(dev)->gen) {

	case 7:

	case 6:

		ret = sandybridge_write_fence_reg(obj);

		break;

	case 5:

	case 4:

		ret = i965_write_fence_reg(obj);

		break;

	case 3:

		ret = i915_write_fence_reg(obj);

		break;

	case 2:

		ret = i830_write_fence_reg(obj);

		break;

	}



	return ret;

	i915_gem_write_fence(dev, reg - dev_priv->fence_regs, obj);

	return 0;

}



/**