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Commit 9858425c authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: gmch: set SR WMs to valid values before enabling them 



Atm it's possible that we enable the memory self-refresh mode before the
watermark levels used by this mode are programmed with valid values. So
move the enabling after we programmed the WM levels.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: default avatarDeepak <S&lt;deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5209b1f4

drivers/gpu/drm/i915/intel_pm.c

+18 −3
Original line number Diff line number Diff line
@@ -1360,6 +1360,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc) 
	int plane_sr, cursor_sr;

	int ignore_plane_sr, ignore_cursor_sr;

	unsigned int enabled = 0;

	bool cxsr_enabled;



	vlv_update_drain_latency(dev);
@@ -1386,8 +1387,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc) 
			     &valleyview_wm_info,

			     &valleyview_cursor_wm_info,

			     &ignore_plane_sr, &cursor_sr)) {

		intel_set_memory_cxsr(dev_priv, true);

		cxsr_enabled = true;

	} else {

		cxsr_enabled = false;

		intel_set_memory_cxsr(dev_priv, false);

		plane_sr = cursor_sr = 0;

	}
@@ -1408,6 +1410,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc) 
	I915_WRITE(DSPFW3,

		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |

		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));



	if (cxsr_enabled)

		intel_set_memory_cxsr(dev_priv, true);

}



static void g4x_update_wm(struct drm_crtc *crtc)
@@ -1418,6 +1423,7 @@ static void g4x_update_wm(struct drm_crtc *crtc) 
	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;

	int plane_sr, cursor_sr;

	unsigned int enabled = 0;

	bool cxsr_enabled;



	if (g4x_compute_wm0(dev, PIPE_A,

			    &g4x_wm_info, latency_ns,
@@ -1437,8 +1443,9 @@ static void g4x_update_wm(struct drm_crtc *crtc) 
			     &g4x_wm_info,

			     &g4x_cursor_wm_info,

			     &plane_sr, &cursor_sr)) {

		intel_set_memory_cxsr(dev_priv, true);

		cxsr_enabled = true;

	} else {

		cxsr_enabled = false;

		intel_set_memory_cxsr(dev_priv, false);

		plane_sr = cursor_sr = 0;

	}
@@ -1460,6 +1467,9 @@ static void g4x_update_wm(struct drm_crtc *crtc) 
	I915_WRITE(DSPFW3,

		   (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |

		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));



	if (cxsr_enabled)

		intel_set_memory_cxsr(dev_priv, true);

}



static void i965_update_wm(struct drm_crtc *unused_crtc)
@@ -1469,6 +1479,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) 
	struct drm_crtc *crtc;

	int srwm = 1;

	int cursor_sr = 16;

	bool cxsr_enabled;



	/* Calc sr entries for one plane configs */

	crtc = single_enabled_crtc(dev);
@@ -1510,8 +1521,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) 
		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "

			      "cursor %d\n", srwm, cursor_sr);



		intel_set_memory_cxsr(dev_priv, true);

		cxsr_enabled = true;

	} else {

		cxsr_enabled = false;

		/* Turn off self refresh if both pipes are enabled */

		intel_set_memory_cxsr(dev_priv, false);

	}
@@ -1525,6 +1537,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) 
	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));

	/* update cursor SR watermark */

	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));



	if (cxsr_enabled)

		intel_set_memory_cxsr(dev_priv, true);

}



static void i9xx_update_wm(struct drm_crtc *unused_crtc)