Staging: Merge 'tidspbridge-2.6.37-rc1' into staging-linus (94fb7c9c) · Commits · e / devices / android_kernel_samsung_universal8895

arch/arm/plat-omap/devices.c

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -284,12 +284,14 @@ void __init omap_dsp_reserve_sdram_memblock(void)
	if (!size)		if (!size)
	return;		return;

	paddr = __memblock_alloc_base(size, SZ_1M, MEMBLOCK_REAL_LIMIT);		paddr = memblock_alloc(size, SZ_1M);
	if (!paddr) {		if (!paddr) {
	pr_err("%s: failed to reserve %x bytes\n",		pr_err("%s: failed to reserve %x bytes\n",
	__func__, size);		__func__, size);
	return;		return;
	}		}
			memblock_free(paddr, size);
			memblock_remove(paddr, size);

	omap_dsp_phys_mempool_base = paddr;		omap_dsp_phys_mempool_base = paddr;
	}		}

drivers/staging/tidspbridge/Kconfig

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -6,7 +6,6 @@ menuconfig TIDSPBRIDGE
	tristate "DSP Bridge driver"		tristate "DSP Bridge driver"
	depends on ARCH_OMAP3		depends on ARCH_OMAP3
	select OMAP_MBOX_FWK		select OMAP_MBOX_FWK
	select OMAP_IOMMU
	help		help
	DSP/BIOS Bridge is designed for platforms that contain a GPP and		DSP/BIOS Bridge is designed for platforms that contain a GPP and
	one or more attached DSPs. The GPP is considered the master or		one or more attached DSPs. The GPP is considered the master or

drivers/staging/tidspbridge/Makefile

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -2,18 +2,19 @@ obj-$(CONFIG_TIDSPBRIDGE) += bridgedriver.o

	libgen = gen/gb.o gen/gs.o gen/gh.o gen/uuidutil.o		libgen = gen/gb.o gen/gs.o gen/gh.o gen/uuidutil.o
	libcore = core/chnl_sm.o core/msg_sm.o core/io_sm.o core/tiomap3430.o \		libcore = core/chnl_sm.o core/msg_sm.o core/io_sm.o core/tiomap3430.o \
	core/tiomap3430_pwr.o core/tiomap_io.o core/dsp-mmu.o \		core/tiomap3430_pwr.o core/tiomap_io.o \
	core/ue_deh.o core/wdt.o core/dsp-clock.o core/sync.o		core/ue_deh.o core/wdt.o core/dsp-clock.o core/sync.o
	libpmgr = pmgr/chnl.o pmgr/io.o pmgr/msg.o pmgr/cod.o pmgr/dev.o pmgr/dspapi.o \		libpmgr = pmgr/chnl.o pmgr/io.o pmgr/msg.o pmgr/cod.o pmgr/dev.o pmgr/dspapi.o \
	pmgr/cmm.o pmgr/dbll.o		pmgr/dmm.o pmgr/cmm.o pmgr/dbll.o
	librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \		librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \
	rmgr/proc.o rmgr/pwr.o rmgr/rmm.o rmgr/strm.o rmgr/dspdrv.o \		rmgr/proc.o rmgr/pwr.o rmgr/rmm.o rmgr/strm.o rmgr/dspdrv.o \
	rmgr/nldr.o rmgr/drv_interface.o		rmgr/nldr.o rmgr/drv_interface.o
	libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o \		libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o \
	dynload/tramp.o		dynload/tramp.o
			libhw = hw/hw_mmu.o

	bridgedriver-y := $(libgen) $(libservices) $(libcore) $(libpmgr) $(librmgr) \		bridgedriver-y := $(libgen) $(libservices) $(libcore) $(libpmgr) $(librmgr) \
	$(libdload)		$(libdload) $(libhw)

	#Machine dependent		#Machine dependent
	ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \		ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \

drivers/staging/tidspbridge/core/_deh.h

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -27,8 +27,9 @@
	struct deh_mgr {		struct deh_mgr {
	struct bridge_dev_context hbridge_context; / Bridge context. */		struct bridge_dev_context hbridge_context; / Bridge context. */
	struct ntfy_object ntfy_obj; / NTFY object */		struct ntfy_object ntfy_obj; / NTFY object */
	};

	int mmu_fault_isr(struct iommu *mmu);		/* MMU Fault DPC */
			struct tasklet_struct dpc_tasklet;
			};

	#endif /* _DEH_ */		#endif /* _DEH_ */

drivers/staging/tidspbridge/core/_tiomap.h

+4 −15

Original line number	Original line	Diff line number	Diff line
	@@ -23,8 +23,8 @@
	#include <plat/clockdomain.h>		#include <plat/clockdomain.h>
	#include <mach-omap2/prm-regbits-34xx.h>		#include <mach-omap2/prm-regbits-34xx.h>
	#include <mach-omap2/cm-regbits-34xx.h>		#include <mach-omap2/cm-regbits-34xx.h>
	#include <dspbridge/dsp-mmu.h>
	#include <dspbridge/devdefs.h>		#include <dspbridge/devdefs.h>
			#include <hw_defs.h>
	#include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */		#include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */
	#include <dspbridge/sync.h>		#include <dspbridge/sync.h>
	#include <dspbridge/clk.h>		#include <dspbridge/clk.h>
	@@ -306,18 +306,6 @@ static const struct bpwr_clk_t bpwr_clks[] = {

	#define CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index)))		#define CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index)))

	struct shm_segs {
	u32 seg0_da;
	u32 seg0_pa;
	u32 seg0_va;
	u32 seg0_size;
	u32 seg1_da;
	u32 seg1_pa;
	u32 seg1_va;
	u32 seg1_size;
	};


	/* This Bridge driver's device context: */		/* This Bridge driver's device context: */
	struct bridge_dev_context {		struct bridge_dev_context {
	struct dev_object hdev_obj; / Handle to Bridge device object. */		struct dev_object hdev_obj; / Handle to Bridge device object. */
	@@ -328,6 +316,7 @@ struct bridge_dev_context {
	*/		*/
	u32 dw_dsp_ext_base_addr; /* See the comment above */		u32 dw_dsp_ext_base_addr; /* See the comment above */
	u32 dw_api_reg_base; /* API mem map'd registers */		u32 dw_api_reg_base; /* API mem map'd registers */
			void __iomem dw_dsp_mmu_base; / DSP MMU Mapped registers */
	u32 dw_api_clk_base; /* CLK Registers */		u32 dw_api_clk_base; /* CLK Registers */
	u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */		u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */
	u32 dw_public_rhea; /* Pub Rhea */		u32 dw_public_rhea; /* Pub Rhea */
	@@ -339,8 +328,7 @@ struct bridge_dev_context {
	u32 dw_internal_size; /* Internal memory size */		u32 dw_internal_size; /* Internal memory size */

	struct omap_mbox mbox; / Mail box handle */		struct omap_mbox mbox; / Mail box handle */
	struct iommu dsp_mmu; / iommu for iva2 handler */
	struct shm_segs sh_s;
	struct cfg_hostres resources; / Host Resources */		struct cfg_hostres resources; / Host Resources */

	/*		/*
	@@ -353,6 +341,7 @@ struct bridge_dev_context {

	/* TC Settings */		/* TC Settings */
	bool tc_word_swap_on; /* Traffic Controller Word Swap */		bool tc_word_swap_on; /* Traffic Controller Word Swap */
			struct pg_table_attrs *pt_attrs;
	u32 dsp_per_clks;		u32 dsp_per_clks;
	};		};