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Commit 8ffbc01e authored by Clemens Ladisch's avatar Clemens Ladisch Committed by Jaroslav Kysela
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[ALSA] cmipci: reorganize set_dac_channels() 



By reorganizing the code that sets the CHB3DxC bits we can not only
simplify this code but also fix the bug where the CHB3D8C bit was not
reset when playing a stereo stream after a 7.1 stream.

Signed-off-by: default avatarClemens Ladisch <clemens@ladisch.de>
Signed-off-by: default avatarJaroslav Kysela <perex@suse.cz>
parent 35add1c2

sound/pci/cmipci.c

+19 −30
Original line number Original line Diff line number Diff line
@@ -738,48 +738,37 @@ static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { 
static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)

static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)

{

{

	if (channels > 2) {

	if (channels > 2) {

		if (! cm->can_multi_ch)

		if (!cm->can_multi_ch || !rec->ch)

			return -EINVAL;

			return -EINVAL;

		if (rec->fmt != 0x03) /* stereo 16bit only */

		if (rec->fmt != 0x03) /* stereo 16bit only */

			return -EINVAL;

			return -EINVAL;

	}





	if (cm->can_multi_ch) {

		spin_lock_irq(&cm->reg_lock);

		spin_lock_irq(&cm->reg_lock);

		if (channels > 2) {

			snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);

			snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);

			snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);

			snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);

		if (channels > 4) {

			snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);

			snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);

		} else {

			snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);

			snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);

		}

		if (channels >= 6) {

			snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);

			snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);

		} else {

		} else {

			snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);

			snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);

			snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);

			snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);

		}

		}

		if (cm->chip_version == 68) {

		if (channels == 8)

			if (channels == 8) {

			snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);

			snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);

			} else {

		else

			snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);

			snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);

			}

		if (channels == 6) {

		}

			snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);

		spin_unlock_irq(&cm->reg_lock);

			snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);



		} else {

		} else {

		if (cm->can_multi_ch) {

			spin_lock_irq(&cm->reg_lock);

			snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);

			snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);

			snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);

			snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);

			snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);

			snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);

			snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);

			snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);

			spin_unlock_irq(&cm->reg_lock);

		}

		}

		if (channels == 4)

			snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);

		else

			snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);

		spin_unlock_irq(&cm->reg_lock);

	}

	}

	return 0;

	return 0;

}

}