Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8e9cc80a authored Nov 25, 2013 by Peter De Schrijver

clk: tegra: use pll_ref as the pll_e parent



Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

parent 04edb099

drivers/clk/tegra/clk-pll.c

+5 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1704,11 +1704,13 @@ struct clk tegra_clk_register_plle_tegra114(const char name,
	val_aux = pll_readl(pll_params->aux_reg, pll);		val_aux = pll_readl(pll_params->aux_reg, pll);

	if (val & PLL_BASE_ENABLE) {		if (val & PLL_BASE_ENABLE) {
	if (!(val_aux & PLLE_AUX_PLLRE_SEL))		if ((val_aux & PLLE_AUX_PLLRE_SEL) \|\|
			(val_aux & PLLE_AUX_PLLP_SEL))
	WARN(1, "pll_e enabled with unsupported parent %s\n",		WARN(1, "pll_e enabled with unsupported parent %s\n",
	(val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");		(val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
			"pll_re_vco");
	} else {		} else {
	val_aux \|= PLLE_AUX_PLLRE_SEL;		val_aux &= ~(PLLE_AUX_PLLRE_SEL \| PLLE_AUX_PLLP_SEL);
	pll_writel(val, pll_params->aux_reg, pll);		pll_writel(val, pll_params->aux_reg, pll);
	}		}

drivers/clk/tegra/clk-tegra114.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -637,6 +637,7 @@ static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
	/* PLLE special case: use cpcon field to store cml divider value */		/* PLLE special case: use cpcon field to store cml divider value */
	{336000000, 100000000, 100, 21, 16, 11},		{336000000, 100000000, 100, 21, 16, 11},
	{312000000, 100000000, 200, 26, 24, 13},		{312000000, 100000000, 200, 26, 24, 13},
			{12000000, 100000000, 200, 1, 24, 13},
	{0, 0, 0, 0, 0, 0},		{0, 0, 0, 0, 0, 0},
	};		};

	@@ -1301,7 +1302,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
	clks[TEGRA114_CLK_PLL_RE_OUT] = clk;		clks[TEGRA114_CLK_PLL_RE_OUT] = clk;

	/* PLLE */		/* PLLE */
	clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",		clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
	clk_base, 0, 100000000, &pll_e_params,		clk_base, 0, 100000000, &pll_e_params,
	pll_e_freq_table, NULL);		pll_e_freq_table, NULL);
	clk_register_clkdev(clk, "pll_e_out0", NULL);		clk_register_clkdev(clk, "pll_e_out0", NULL);