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Commit 8cf1a3de authored by Kan Liang's avatar Kan Liang Committed by Ingo Molnar
Browse files

perf/x86/intel/uncore: Fix CBOX bit wide and UBOX reg on Haswell-EP 

CBOX counters are increased to 48b on HSX.

Correct the MSR address for HSWEP_U_MSR_PMON_CTR0 and
HSWEP_U_MSR_PMON_CTL0.

See specification in:
http://www.intel.com/content/www/us/en/processors/xeon/


xeon-e5-v3-uncore-performance-monitoring.html

Signed-off-by: default avatarKan Liang <kan.liang@intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1432645835-7918-1-git-send-email-kan.liang@intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 37ef1647

arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c

+3 −3
Original line number Diff line number Diff line
@@ -164,8 +164,8 @@ 
				((1ULL << (n)) - 1)))



/* Haswell-EP Ubox */

#define HSWEP_U_MSR_PMON_CTR0			0x705

#define HSWEP_U_MSR_PMON_CTL0			0x709

#define HSWEP_U_MSR_PMON_CTR0			0x709

#define HSWEP_U_MSR_PMON_CTL0			0x705

#define HSWEP_U_MSR_PMON_FILTER			0x707



#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL		0x703
@@ -1914,7 +1914,7 @@ static struct intel_uncore_type hswep_uncore_cbox = { 
	.name			= "cbox",

	.num_counters		= 4,

	.num_boxes		= 18,

	.perf_ctr_bits		= 44,

	.perf_ctr_bits		= 48,

	.event_ctl		= HSWEP_C0_MSR_PMON_CTL0,

	.perf_ctr		= HSWEP_C0_MSR_PMON_CTR0,

	.event_mask		= SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,