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Commit 867f503d authored by Grant Likely's avatar Grant Likely
Browse files

Merge branch 'msm-move-gpio' of git://codeaurora.org/quic/kernel/davidb/linux-msm into gpio/next 

Conflicts:
	drivers/gpio/Kconfig
	drivers/gpio/Makefile
parents 5b8ce5eb 1a5ab4b3

arch/arm/mach-msm/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ config ARCH_MSM7X00A 
	select MSM_SMD

	select MSM_SMD_PKG3

	select CPU_V6

	select GPIO_MSM_V1

	select MSM_PROC_COMM

	select HAS_MSM_DEBUG_UART_PHYS
@@ -22,6 +23,7 @@ config ARCH_MSM7X30 
	select MSM_VIC

	select CPU_V7

	select MSM_GPIOMUX

	select GPIO_MSM_V1

	select MSM_PROC_COMM

	select HAS_MSM_DEBUG_UART_PHYS
@@ -33,6 +35,7 @@ config ARCH_QSD8X50 
	select MSM_VIC

	select CPU_V7

	select MSM_GPIOMUX

	select GPIO_MSM_V1

	select MSM_PROC_COMM

	select HAS_MSM_DEBUG_UART_PHYS
@@ -44,6 +47,7 @@ config ARCH_MSM8X60 
	select ARM_GIC

	select CPU_V7

	select MSM_V2_TLMM

	select GPIO_MSM_V2

	select MSM_GPIOMUX

	select MSM_SCM if SMP

arch/arm/mach-msm/Makefile

+0 −8
Original line number Diff line number Diff line
@@ -29,11 +29,3 @@ obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o 
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o

obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o

obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
 
ifdef CONFIG_MSM_V2_TLMM

ifndef CONFIG_ARCH_MSM8960

# TODO: TLMM Mapping issues need to be resolved

obj-y	+= gpio-v2.o

endif

else

obj-y	+= gpio.o

endif

arch/arm/mach-msm/gpio_hw.h

deleted100644 → 0
+0 −278
Original line number Diff line number Diff line 
/* arch/arm/mach-msm/gpio_hw.h

 *

 * Copyright (C) 2007 Google, Inc.

 * Author: Brian Swetland <swetland@google.com>

 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H

#define __ARCH_ARM_MACH_MSM_GPIO_HW_H



#include <mach/msm_iomap.h>



/* see 80-VA736-2 Rev C pp 695-751

**

** These are actually the *shadow* gpio registers, since the

** real ones (which allow full access) are only available to the

** ARM9 side of the world.

**

** Since the _BASE need to be page-aligned when we're mapping them

** to virtual addresses, adjust for the additional offset in these

** macros.

*/



#if defined(CONFIG_ARCH_MSM7X30)

#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))

#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))

#else

#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))

#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))

#endif



#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\

    defined(CONFIG_ARCH_MSM7X27)



/* output value */

#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0  */

#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16 */

#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43 */

#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68 */

#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 106-95 */

#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)  /* gpio 107-121 */



/* same pin map as above, output enable */

#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)

#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)

#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)

#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)

#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)

#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)



/* same pin map as above, input read */

#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)

#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)

#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)

#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)

#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)

#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)



/* same pin map as above, 1=edge 0=level interrup */

#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)

#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)

#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)

#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)

#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)

#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)



/* same pin map as above, 1=positive 0=negative */

#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)

#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)

#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)

#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)

#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)

#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)



/* same pin map as above, interrupt enable */

#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)

#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)

#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)

#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)

#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0x8C)

#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xB8)



/* same pin map as above, write 1 to clear interrupt */

#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0x90)

#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)

#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0x94)

#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0x98)

#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0x9C)

#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xB4)



/* same pin map as above, 1=interrupt pending */

#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xA0)

#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)

#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xA4)

#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xA8)

#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xAC)

#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0xB0)



#endif



#if defined(CONFIG_ARCH_QSD8X50)

/* output value */

#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0   */

#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16  */

#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43  */

#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68  */

#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 103-95  */

#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x10)  /* gpio 121-104 */

#define MSM_GPIO_OUT_6         MSM_GPIO1_REG(0x14)  /* gpio 152-122 */

#define MSM_GPIO_OUT_7         MSM_GPIO1_REG(0x18)  /* gpio 164-153 */



/* same pin map as above, output enable */

#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x20)

#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)

#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x24)

#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x28)

#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x2C)

#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x30)

#define MSM_GPIO_OE_6          MSM_GPIO1_REG(0x34)

#define MSM_GPIO_OE_7          MSM_GPIO1_REG(0x38)



/* same pin map as above, input read */

#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x50)

#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)

#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x54)

#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x58)

#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x5C)

#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x60)

#define MSM_GPIO_IN_6          MSM_GPIO1_REG(0x64)

#define MSM_GPIO_IN_7          MSM_GPIO1_REG(0x68)



/* same pin map as above, 1=edge 0=level interrup */

#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x70)

#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)

#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x74)

#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x78)

#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x7C)

#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0x80)

#define MSM_GPIO_INT_EDGE_6    MSM_GPIO1_REG(0x84)

#define MSM_GPIO_INT_EDGE_7    MSM_GPIO1_REG(0x88)



/* same pin map as above, 1=positive 0=negative */

#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x90)

#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)

#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x94)

#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x98)

#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x9C)

#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xA0)

#define MSM_GPIO_INT_POS_6     MSM_GPIO1_REG(0xA4)

#define MSM_GPIO_INT_POS_7     MSM_GPIO1_REG(0xA8)



/* same pin map as above, interrupt enable */

#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0xB0)

#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)

#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0xB4)

#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0xB8)

#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0xBC)

#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xC0)

#define MSM_GPIO_INT_EN_6      MSM_GPIO1_REG(0xC4)

#define MSM_GPIO_INT_EN_7      MSM_GPIO1_REG(0xC8)



/* same pin map as above, write 1 to clear interrupt */

#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0xD0)

#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)

#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0xD4)

#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0xD8)

#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0xDC)

#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xE0)

#define MSM_GPIO_INT_CLEAR_6   MSM_GPIO1_REG(0xE4)

#define MSM_GPIO_INT_CLEAR_7   MSM_GPIO1_REG(0xE8)



/* same pin map as above, 1=interrupt pending */

#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xF0)

#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)

#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xF4)

#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xF8)

#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xFC)

#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0x100)

#define MSM_GPIO_INT_STATUS_6  MSM_GPIO1_REG(0x104)

#define MSM_GPIO_INT_STATUS_7  MSM_GPIO1_REG(0x108)



#endif



#if defined(CONFIG_ARCH_MSM7X30)



/* output value */

#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)   /* gpio  15-0   */

#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)   /* gpio  43-16  */

#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)   /* gpio  67-44  */

#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)   /* gpio  94-68  */

#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)   /* gpio 106-95  */

#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)   /* gpio 133-107 */

#define MSM_GPIO_OUT_6         MSM_GPIO1_REG(0xC4)   /* gpio 150-134 */

#define MSM_GPIO_OUT_7         MSM_GPIO1_REG(0x214)  /* gpio 181-151 */



/* same pin map as above, output enable */

#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)

#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)

#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)

#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)

#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)

#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)

#define MSM_GPIO_OE_6          MSM_GPIO1_REG(0xC8)

#define MSM_GPIO_OE_7          MSM_GPIO1_REG(0x218)



/* same pin map as above, input read */

#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)

#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)

#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)

#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)

#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)

#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)

#define MSM_GPIO_IN_6          MSM_GPIO1_REG(0xCC)

#define MSM_GPIO_IN_7          MSM_GPIO1_REG(0x21C)



/* same pin map as above, 1=edge 0=level interrup */

#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)

#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)

#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)

#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)

#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)

#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)

#define MSM_GPIO_INT_EDGE_6    MSM_GPIO1_REG(0xD0)

#define MSM_GPIO_INT_EDGE_7    MSM_GPIO1_REG(0x240)



/* same pin map as above, 1=positive 0=negative */

#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)

#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)

#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)

#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)

#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)

#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)

#define MSM_GPIO_INT_POS_6     MSM_GPIO1_REG(0xD4)

#define MSM_GPIO_INT_POS_7     MSM_GPIO1_REG(0x228)



/* same pin map as above, interrupt enable */

#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)

#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)

#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)

#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)

#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0x8C)

#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xB8)

#define MSM_GPIO_INT_EN_6      MSM_GPIO1_REG(0xD8)

#define MSM_GPIO_INT_EN_7      MSM_GPIO1_REG(0x22C)



/* same pin map as above, write 1 to clear interrupt */

#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0x90)

#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)

#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0x94)

#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0x98)

#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0x9C)

#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xB4)

#define MSM_GPIO_INT_CLEAR_6   MSM_GPIO1_REG(0xDC)

#define MSM_GPIO_INT_CLEAR_7   MSM_GPIO1_REG(0x230)



/* same pin map as above, 1=interrupt pending */

#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xA0)

#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)

#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xA4)

#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xA8)

#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xAC)

#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0xB0)

#define MSM_GPIO_INT_STATUS_6  MSM_GPIO1_REG(0xE0)

#define MSM_GPIO_INT_STATUS_7  MSM_GPIO1_REG(0x234)



#endif



#endif

arch/arm/mach-msm/gpiomux.h

+1 −16
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 


#include <linux/bitops.h>

#include <linux/errno.h>

#include <mach/msm_gpiomux.h>



#if defined(CONFIG_MSM_V2_TLMM)

#include "gpiomux-v2.h"
@@ -71,12 +72,6 @@ enum { 
 */

extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];



/* Increment a gpio's reference count, possibly activating the line. */

int __must_check msm_gpiomux_get(unsigned gpio);



/* Decrement a gpio's reference count, possibly suspending the line. */

int msm_gpiomux_put(unsigned gpio);



/* Install a new configuration to the gpio line.  To avoid overwriting

 * a configuration, leave the VALID bit out.

 */
@@ -94,16 +89,6 @@ int msm_gpiomux_write(unsigned gpio, 
 */

void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);

#else

static inline int __must_check msm_gpiomux_get(unsigned gpio)

{

	return -ENOSYS;

}



static inline int msm_gpiomux_put(unsigned gpio)

{

	return -ENOSYS;

}



static inline int msm_gpiomux_write(unsigned gpio,

				    gpiomux_config_t active,

				    gpiomux_config_t suspended)

arch/arm/mach-msm/include/mach/msm_gpiomux.h

0 → 100644
+38 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _LINUX_MSM_GPIOMUX_H

#define _LINUX_MSM_GPIOMUX_H



#ifdef CONFIG_MSM_GPIOMUX



/* Increment a gpio's reference count, possibly activating the line. */

int __must_check msm_gpiomux_get(unsigned gpio);



/* Decrement a gpio's reference count, possibly suspending the line. */

int msm_gpiomux_put(unsigned gpio);



#else



static inline int __must_check msm_gpiomux_get(unsigned gpio)

{

	return -ENOSYS;

}



static inline int msm_gpiomux_put(unsigned gpio)

{

	return -ENOSYS;

}



#endif



#endif /* _LINUX_MSM_GPIOMUX_H */