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Commit 86576fbe authored by Tomasz Figa's avatar Tomasz Figa Committed by Kukjin Kim
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clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider 



The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Acked-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent a98e3190

drivers/clk/samsung/clk-exynos4.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { 
	DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),

	DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),

	DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),

	DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),

	DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),

	DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),

	DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),

	DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,

			CLK_SET_RATE_PARENT, 0),

	DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),

	DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),

	DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),

	DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),

	DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),

	DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),