Commit 85a16ef6 authored Aug 12, 2014 by Stephane Eranian Committed by Ingo Molnar Aug 13, 2014

perf/x86/uncore: Export basic memory events for IVT IMC PMU

This patch exposes two basic events for Ivytown IMC uncore PMU:

- cas_count_read: number of full-cache line reads to memory controller
- cas_count_write: number of full-cache line writes to memory controller

Those events use the same encoding as for SNB-EP, so reuse the same
event table. See specification in:

http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf



By aggregating all the read and write events from all the memory controllers
of each processor socket, one can determine the total memory bandwidth utilization.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20140812060031.GA25239@quad


Cc: zheng.z.yan@intel.com
Cc: ak@linux.intel.com
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent c8aab2e0

arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -1422,6 +1422,7 @@ static struct intel_uncore_type ivt_uncore_imc = {
		.fixed_ctr_bits = 48,
		.fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
		.fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
		.event_descs = snbep_uncore_imc_events,
		IVT_UNCORE_PCI_COMMON_INIT(),
		};