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Commit 7d44d2ba authored by Jongpill Lee's avatar Jongpill Lee Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Add PMU table for EXYNOS5250 



This patch adds pmu table setting feature for EXYNOS5250.

Signed-off-by: default avatarJongpill Lee <boyko.lee@samsung.com>
[kgene.kim@samsung.com: re-worked on top of v3.4-rc7]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent c9347101

arch/arm/mach-exynos/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ obj-$(CONFIG_PM) += pm.o 
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o

obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o



obj-$(CONFIG_ARCH_EXYNOS4)	+= pmu.o

obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o



obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o

arch/arm/mach-exynos/cpuidle.c

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, 
	exynos4_set_wakeupmask();



	/* Set value of power down register for aftr mode */

	exynos4_sys_powerdown_conf(SYS_AFTR);

	exynos_sys_powerdown_conf(SYS_AFTR);



	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);

	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);

arch/arm/mach-exynos/include/mach/pmu.h

+2 −2
Original line number Diff line number Diff line
@@ -23,12 +23,12 @@ enum sys_powerdown { 
};



extern unsigned long l2x0_regs_phys;

struct exynos4_pmu_conf {

struct exynos_pmu_conf {

	void __iomem *reg;

	unsigned int val[NUM_SYS_POWERDOWN];

};



extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);

extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);

extern void s3c_cpu_resume(void);



#endif /* __ASM_ARCH_PMU_H */

arch/arm/mach-exynos/include/mach/regs-pmu.h

+137 −4
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h

 *

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

/*

 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4 - Power management unit definition

 * EXYNOS - Power management unit definition

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -226,4 +225,138 @@ 
#define S5P_DIS_IRQ_CORE3			S5P_PMUREG(0x1034)

#define S5P_DIS_IRQ_CENTRAL3			S5P_PMUREG(0x1038)



/* For EXYNOS5 */



#define EXYNOS5_USB_CFG						S5P_PMUREG(0x0230)



#define EXYNOS5_ARM_CORE0_SYS_PWR_REG				S5P_PMUREG(0x1000)

#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1004)

#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1008)

#define EXYNOS5_ARM_CORE1_SYS_PWR_REG				S5P_PMUREG(0x1010)

#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1014)

#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1018)

#define EXYNOS5_FSYS_ARM_SYS_PWR_REG				S5P_PMUREG(0x1040)

#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1048)

#define EXYNOS5_ISP_ARM_SYS_PWR_REG				S5P_PMUREG(0x1050)

#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1054)

#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1058)

#define EXYNOS5_ARM_COMMON_SYS_PWR_REG				S5P_PMUREG(0x1080)

#define EXYNOS5_ARM_L2_SYS_PWR_REG				S5P_PMUREG(0x10C0)

#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG			S5P_PMUREG(0x1100)

#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG			S5P_PMUREG(0x1104)

#define EXYNOS5_CMU_RESET_SYS_PWR_REG				S5P_PMUREG(0x110C)

#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1120)

#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1124)

#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x112C)

#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG			S5P_PMUREG(0x1130)

#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG			S5P_PMUREG(0x1134)

#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG			S5P_PMUREG(0x1138)

#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1140)

#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1144)

#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1148)

#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x114C)

#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1150)

#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1154)

#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG			S5P_PMUREG(0x1164)

#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG			S5P_PMUREG(0x1170)

#define EXYNOS5_TOP_BUS_SYS_PWR_REG				S5P_PMUREG(0x1180)

#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG			S5P_PMUREG(0x1184)

#define EXYNOS5_TOP_PWR_SYS_PWR_REG				S5P_PMUREG(0x1188)

#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1190)

#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x1194)

#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1198)

#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG				S5P_PMUREG(0x11A0)

#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG				S5P_PMUREG(0x11A4)

#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x11B0)

#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x11B4)

#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG				S5P_PMUREG(0x11C0)

#define EXYNOS5_G2D_MEM_SYS_PWR_REG				S5P_PMUREG(0x11C8)

#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG				S5P_PMUREG(0x11CC)

#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D0)

#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D4)

#define EXYNOS5_SECSS_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D8)

#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG				S5P_PMUREG(0x11DC)

#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E0)

#define EXYNOS5_INTROM_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E4)

#define EXYNOS5_JPEG_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E8)

#define EXYNOS5_HSI_MEM_SYS_PWR_REG				S5P_PMUREG(0x11EC)

#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG				S5P_PMUREG(0x11F4)

#define EXYNOS5_SATA_MEM_SYS_PWR_REG				S5P_PMUREG(0x11FC)

#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG			S5P_PMUREG(0x1200)

#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG			S5P_PMUREG(0x1204)

#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG		S5P_PMUREG(0x1208)

#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG			S5P_PMUREG(0x1220)

#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG			S5P_PMUREG(0x1224)

#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG			S5P_PMUREG(0x1228)

#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG			S5P_PMUREG(0x122C)

#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG			S5P_PMUREG(0x1230)

#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG			S5P_PMUREG(0x1234)

#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG			S5P_PMUREG(0x1238)

#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x123C)

#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG			S5P_PMUREG(0x1240)

#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x1250)

#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG				S5P_PMUREG(0x1260)

#define EXYNOS5_XUSBXTI_SYS_PWR_REG				S5P_PMUREG(0x1280)

#define EXYNOS5_XXTI_SYS_PWR_REG				S5P_PMUREG(0x1284)

#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG			S5P_PMUREG(0x12C0)

#define EXYNOS5_GPIO_MODE_SYS_PWR_REG				S5P_PMUREG(0x1300)

#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1320)

#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG			S5P_PMUREG(0x1340)

#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG			S5P_PMUREG(0x1344)

#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG			S5P_PMUREG(0x1348)

#define EXYNOS5_GSCL_SYS_PWR_REG				S5P_PMUREG(0x1400)

#define EXYNOS5_ISP_SYS_PWR_REG					S5P_PMUREG(0x1404)

#define EXYNOS5_MFC_SYS_PWR_REG					S5P_PMUREG(0x1408)

#define EXYNOS5_G3D_SYS_PWR_REG					S5P_PMUREG(0x140C)

#define EXYNOS5_DISP1_SYS_PWR_REG				S5P_PMUREG(0x1414)

#define EXYNOS5_MAU_SYS_PWR_REG					S5P_PMUREG(0x1418)

#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1480)

#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG			S5P_PMUREG(0x1484)

#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG			S5P_PMUREG(0x1488)

#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG			S5P_PMUREG(0x148C)

#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1494)

#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG			S5P_PMUREG(0x1498)

#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG			S5P_PMUREG(0x14C0)

#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG			S5P_PMUREG(0x14C4)

#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG			S5P_PMUREG(0x14C8)

#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG			S5P_PMUREG(0x14CC)

#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG			S5P_PMUREG(0x14D4)

#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG			S5P_PMUREG(0x14D8)

#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1580)

#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG			S5P_PMUREG(0x1584)

#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG			S5P_PMUREG(0x1588)

#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG			S5P_PMUREG(0x158C)

#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1594)

#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG			S5P_PMUREG(0x1598)



#define EXYNOS5_ARM_CORE0_OPTION				S5P_PMUREG(0x2008)

#define EXYNOS5_ARM_CORE1_OPTION				S5P_PMUREG(0x2088)

#define EXYNOS5_FSYS_ARM_OPTION					S5P_PMUREG(0x2208)

#define EXYNOS5_ISP_ARM_OPTION					S5P_PMUREG(0x2288)

#define EXYNOS5_ARM_COMMON_OPTION				S5P_PMUREG(0x2408)

#define EXYNOS5_TOP_PWR_OPTION					S5P_PMUREG(0x2C48)

#define EXYNOS5_TOP_PWR_SYSMEM_OPTION				S5P_PMUREG(0x2CC8)

#define EXYNOS5_JPEG_MEM_OPTION					S5P_PMUREG(0x2F48)

#define EXYNOS5_GSCL_STATUS					S5P_PMUREG(0x4004)

#define EXYNOS5_ISP_STATUS					S5P_PMUREG(0x4024)

#define EXYNOS5_GSCL_OPTION					S5P_PMUREG(0x4008)

#define EXYNOS5_ISP_OPTION					S5P_PMUREG(0x4028)

#define EXYNOS5_MFC_OPTION					S5P_PMUREG(0x4048)

#define EXYNOS5_G3D_CONFIGURATION				S5P_PMUREG(0x4060)

#define EXYNOS5_G3D_STATUS					S5P_PMUREG(0x4064)

#define EXYNOS5_G3D_OPTION					S5P_PMUREG(0x4068)

#define EXYNOS5_DISP1_OPTION					S5P_PMUREG(0x40A8)

#define EXYNOS5_MAU_OPTION					S5P_PMUREG(0x40C8)



#define EXYNOS5_USE_SC_FEEDBACK					(1 << 1)

#define EXYNOS5_USE_SC_COUNTER					(1 << 0)



#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL			(1 << 2)

#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN			(1 << 7)



#define EXYNOS5_OPTION_USE_STANDBYWFE				(1 << 24)

#define EXYNOS5_OPTION_USE_STANDBYWFI				(1 << 16)



#define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)



#endif /* __ASM_ARCH_REGS_PMU_H */

arch/arm/mach-exynos/pm.c

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static void exynos_pm_prepare(void) 


	/* Set value of power down register for sleep mode */



	exynos4_sys_powerdown_conf(SYS_SLEEP);

	exynos_sys_powerdown_conf(SYS_SLEEP);

	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);



	/* ensure at least INFORM0 has the resume address */