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Commit 786a7828 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next 

this is the second pull request for 3.15 radeon changes. Highlights this time:
- Better VRAM usage
- VM page table rework
- Enabling different UVD clocks again
- Some general cleanups and improvements

* 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: remove struct radeon_bo_list
  drm/radeon: drop non blocking allocations from sub allocator
  drm/radeon: remove global vm lock
  drm/radeon: use normal BOs for the page tables v4
  drm/radeon: further cleanup vm flushing & fencing
  drm/radeon: separate gart and vm functions
  drm/radeon: fix VCE suspend/resume
  drm/radeon: fix missing bo reservation
  drm/radeon: limit how much memory TTM can move per IB according to VRAM usage
  drm/radeon: validate relocations in the order determined by userspace v3
  drm/radeon: add buffers to the LRU list from smallest to largest
  drm/radeon: deduplicate code in radeon_gem_busy_ioctl
  drm/radeon: track memory statistics about VRAM and GTT usage and buffer moves v2
  drm/radeon: add a way to get and set initial buffer domains v2
  drm/radeon: use variable UVD clocks
  drm/radeon: cleanup the fence ring locking code
  drm/radeon: improve ring lockup detection code v2
parents 4d33f3aa df0af440

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \

	ci_dpm.o dce6_afmt.o

	ci_dpm.o dce6_afmt.o radeon_vm.o



# add async DMA block

radeon-y += \

drivers/gpu/drm/radeon/evergreen_cs.c

+105 −105

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drivers/gpu/drm/radeon/r100.c

+20 −20

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drivers/gpu/drm/radeon/r200.c

+10 −10
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
		track->zb.robj = reloc->robj;

		track->zb.offset = idx_value;

		track->zb_dirty = true;

		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);

		ib[idx] = idx_value + ((u32)reloc->gpu_offset);

		break;

	case RADEON_RB3D_COLOROFFSET:

		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
@@ -198,7 +198,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
		track->cb[0].robj = reloc->robj;

		track->cb[0].offset = idx_value;

		track->cb_dirty = true;

		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);

		ib[idx] = idx_value + ((u32)reloc->gpu_offset);

		break;

	case R200_PP_TXOFFSET_0:

	case R200_PP_TXOFFSET_1:
@@ -215,16 +215,16 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
			return r;

		}

		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

			if (reloc->tiling_flags & RADEON_TILING_MACRO)

				tile_flags |= R200_TXO_MACRO_TILE;

			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)

			if (reloc->tiling_flags & RADEON_TILING_MICRO)

				tile_flags |= R200_TXO_MICRO_TILE;



			tmp = idx_value & ~(0x7 << 2);

			tmp |= tile_flags;

			ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);

			ib[idx] = tmp + ((u32)reloc->gpu_offset);

		} else

			ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);

			ib[idx] = idx_value + ((u32)reloc->gpu_offset);

		track->textures[i].robj = reloc->robj;

		track->tex_dirty = true;

		break;
@@ -268,7 +268,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
			return r;

		}

		track->textures[i].cube_info[face - 1].offset = idx_value;

		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);

		ib[idx] = idx_value + ((u32)reloc->gpu_offset);

		track->textures[i].cube_info[face - 1].robj = reloc->robj;

		track->tex_dirty = true;

		break;
@@ -287,9 +287,9 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
		}



		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

			if (reloc->tiling_flags & RADEON_TILING_MACRO)

				tile_flags |= RADEON_COLOR_TILE_ENABLE;

			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)

			if (reloc->tiling_flags & RADEON_TILING_MICRO)

				tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;



			tmp = idx_value & ~(0x7 << 16);
@@ -362,7 +362,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
			radeon_cs_dump_packet(p, pkt);

			return r;

		}

		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);

		ib[idx] = idx_value + ((u32)reloc->gpu_offset);

		break;

	case RADEON_PP_CNTL:

		{

drivers/gpu/drm/radeon/r300.c

+16 −16

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