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Commit 770eee1f authored by Stephane Eranian's avatar Stephane Eranian Committed by Ingo Molnar
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perf/x86: Fix data source encoding issues for load latency/precise store 



This patch fixes issues introuduce by Andi's previous patch 'Revamp PEBS'
series.

This patch fixes the following:

 - precise_store_data_hsw() encode the mem op type whenever we can
 - precise_store_data_hsw set the default data source correctly

 - 0 is not a valid init value for data source. Define PERF_MEM_NA as the
   default value

This bug was actually introduced by

    commit 722e76e6
    Author: Stephane Eranian <eranian@google.com>
    Date:   Thu May 15 17:56:44 2014 +0200

        fix Haswell precise store data source encoding

Signed-off-by: default avatarStephane Eranian <eranian@google.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1407785233-32193-4-git-send-email-eranian@google.com


Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: ak@linux.intel.com
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent f3908b8c

arch/x86/kernel/cpu/perf_event_intel_ds.c

+7 −4
Original line number Diff line number Diff line
@@ -113,9 +113,12 @@ static u64 precise_store_data_hsw(struct perf_event *event, u64 status) 
	union perf_mem_data_src dse;

	u64 cfg = event->hw.config & INTEL_ARCH_EVENT_MASK;



	dse.val = 0;

	dse.mem_op = PERF_MEM_OP_NA;

	dse.mem_lvl = PERF_MEM_LVL_NA;

	dse.val = PERF_MEM_NA;



	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)

		dse.mem_op = PERF_MEM_OP_STORE;

	else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)

		dse.mem_op = PERF_MEM_OP_LOAD;



	/*

	 * L1 info only valid for following events:
@@ -126,7 +129,7 @@ static u64 precise_store_data_hsw(struct perf_event *event, u64 status) 
	 * MEM_UOPS_RETIRED.ALL_STORES

	 */

	if (cfg != 0x12d0 && cfg != 0x22d0 && cfg != 0x42d0 && cfg != 0x82d0)

		return dse.mem_lvl;

		return dse.val;



	if (status & 1)

		dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;

include/linux/perf_event.h

+8 −1
Original line number Diff line number Diff line
@@ -608,6 +608,13 @@ struct perf_sample_data { 
	u64				txn;

};



/* default value for data source */

#define PERF_MEM_NA (PERF_MEM_S(OP, NA)   |\

		    PERF_MEM_S(LVL, NA)   |\

		    PERF_MEM_S(SNOOP, NA) |\

		    PERF_MEM_S(LOCK, NA)  |\

		    PERF_MEM_S(TLB, NA))



static inline void perf_sample_data_init(struct perf_sample_data *data,

					 u64 addr, u64 period)

{
@@ -620,7 +627,7 @@ static inline void perf_sample_data_init(struct perf_sample_data *data, 
	data->regs_user.regs = NULL;

	data->stack_user_size = 0;

	data->weight = 0;

	data->data_src.val = 0;

	data->data_src.val = PERF_MEM_NA;

	data->txn = 0;

}