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Commit 72dc53ac authored by Will Deacon's avatar Will Deacon
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ARM: cache: detect VIPT aliasing I-cache on ARMv6 



The current cache detection code does not check for an aliasing
I-cache if the D-cache is found to be VIPT aliasing.

This patch fixes the problem by always checking for an aliasing
I-cache on v6 and later.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent dfc40b24

arch/arm/kernel/setup.c

+8 −7
Original line number Diff line number Diff line
@@ -280,18 +280,19 @@ static void __init cacheid_init(void) 
	if (arch >= CPU_ARCH_ARMv6) {

		if ((cachetype & (7 << 29)) == 4 << 29) {

			/* ARMv7 register format */

			arch = CPU_ARCH_ARMv7;

			cacheid = CACHEID_VIPT_NONALIASING;

			if ((cachetype & (3 << 14)) == 1 << 14)

				cacheid |= CACHEID_ASID_TAGGED;

			else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))

				cacheid |= CACHEID_VIPT_I_ALIASING;

		} else if (cachetype & (1 << 23)) {

			cacheid = CACHEID_VIPT_ALIASING;

		} else {

			arch = CPU_ARCH_ARMv6;

			if (cachetype & (1 << 23))

				cacheid = CACHEID_VIPT_ALIASING;

			else

				cacheid = CACHEID_VIPT_NONALIASING;

			if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6))

				cacheid |= CACHEID_VIPT_I_ALIASING;

		}

		if (cpu_has_aliasing_icache(arch))

			cacheid |= CACHEID_VIPT_I_ALIASING;

	} else {

		cacheid = CACHEID_VIVT;

	}