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Commit 6f492b6d authored by Shiang Tu's avatar Shiang Tu Committed by John W. Linville
Browse files

rt2x00: Add/Modify protection related register definitions 



Make the definition of protection related registers more precisely

Signed-off-by: default avatarShiang Tu <shiang_tu@ralinktech.com>
Acked-by: default avatarHelmut Schaa <helmut.schaa@googlemail.com>
Acked-by: default avatarGertjan van Wingerde <gwingerde@gmail.com>
Signed-off-by: default avatarIvo van Doorn <IvDoorn@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 47715e64

drivers/net/wireless/rt2x00/rt2800.h

+14 −8
Original line number Diff line number Diff line
@@ -1138,8 +1138,8 @@ 
 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)

 * PROTECT_CTRL: Protection control frame type for CCK TX

 *               0:none, 1:RTS/CTS, 2:CTS-to-self

 * PROTECT_NAV: TXOP protection type for CCK TX

 *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect

 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV

 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV

 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow

 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow

 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
@@ -1151,7 +1151,8 @@ 
#define CCK_PROT_CFG			0x1364

#define CCK_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)

#define CCK_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)

#define CCK_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)

#define CCK_PROT_CFG_PROTECT_NAV_SHORT	FIELD32(0x00040000)

#define CCK_PROT_CFG_PROTECT_NAV_LONG	FIELD32(0x00080000)

#define CCK_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)

#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)

#define CCK_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
@@ -1166,7 +1167,8 @@ 
#define OFDM_PROT_CFG			0x1368

#define OFDM_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)

#define OFDM_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)

#define OFDM_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)

#define OFDM_PROT_CFG_PROTECT_NAV_SHORT	FIELD32(0x00040000)

#define OFDM_PROT_CFG_PROTECT_NAV_LONG	FIELD32(0x00080000)

#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)

#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)

#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
@@ -1181,7 +1183,8 @@ 
#define MM20_PROT_CFG			0x136c

#define MM20_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)

#define MM20_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)

#define MM20_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)

#define MM20_PROT_CFG_PROTECT_NAV_SHORT	FIELD32(0x00040000)

#define MM20_PROT_CFG_PROTECT_NAV_LONG	FIELD32(0x00080000)

#define MM20_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)

#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)

#define MM20_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
@@ -1196,7 +1199,8 @@ 
#define MM40_PROT_CFG			0x1370

#define MM40_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)

#define MM40_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)

#define MM40_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)

#define MM40_PROT_CFG_PROTECT_NAV_SHORT	FIELD32(0x00040000)

#define MM40_PROT_CFG_PROTECT_NAV_LONG	FIELD32(0x00080000)

#define MM40_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)

#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)

#define MM40_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
@@ -1211,7 +1215,8 @@ 
#define GF20_PROT_CFG			0x1374

#define GF20_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)

#define GF20_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)

#define GF20_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)

#define GF20_PROT_CFG_PROTECT_NAV_SHORT	FIELD32(0x00040000)

#define GF20_PROT_CFG_PROTECT_NAV_LONG	FIELD32(0x00080000)

#define GF20_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)

#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)

#define GF20_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
@@ -1226,7 +1231,8 @@ 
#define GF40_PROT_CFG			0x1378

#define GF40_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)

#define GF40_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)

#define GF40_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)

#define GF40_PROT_CFG_PROTECT_NAV_SHORT	FIELD32(0x00040000)

#define GF40_PROT_CFG_PROTECT_NAV_LONG	FIELD32(0x00080000)

#define GF40_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)

#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)

#define GF40_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)

drivers/net/wireless/rt2x00/rt2800lib.c

+6 −6
Original line number Diff line number Diff line
@@ -2193,7 +2193,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);

	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2206,7 +2206,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);

	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2219,7 +2219,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);

	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2232,7 +2232,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);

	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2245,7 +2245,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);

	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2258,7 +2258,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);

	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);