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Commit 6f11c69d authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
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ARM: imx: add gpt_3m clk for i.mx6qdl 



Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.

i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.

Signed-off-by: default avatarAnson Huang <b20788@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 69d9a3fe

arch/arm/mach-imx/clk-imx6q.c

+8 −0
Original line number Diff line number Diff line
@@ -245,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);

	clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);

	clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);

	clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);

	if (cpu_is_imx6dl()) {

		clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);

		clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@@ -461,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk[IMX6QDL_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);

	clk[IMX6QDL_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);



	/*

	 * The gpt_3m clock is not available on i.MX6Q TO1.0.  Let's point it

	 * to clock gpt_ipg_per to ease the gpt driver code.

	 */

	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)

		clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];



	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_data.clks = clk;

include/dt-bindings/clock/imx6qdl-clock.h

+2 −1
Original line number Diff line number Diff line
@@ -247,6 +247,7 @@ 
#define IMX6QDL_PLL5_BYPASS			234

#define IMX6QDL_PLL6_BYPASS			235

#define IMX6QDL_PLL7_BYPASS			236

#define IMX6QDL_CLK_END				237

#define IMX6QDL_CLK_GPT_3M			237

#define IMX6QDL_CLK_END				238



#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */