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Commit 6dece0eb authored by Scott Wood's avatar Scott Wood Committed by Benjamin Herrenschmidt
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powerpc/32: Pass device tree address as u64 to machine_init



u64 is used rather than phys_addr_t to keep things simple, as
this is called from assembly code.

Update callers to pass a 64-bit address in r3/r4.  Other unused
register assignments that were once parameters to machine_init
are dropped.

For FSL BookE, look up the physical address of the device tree from the
effective address passed in r3 by the loader.  This is required for
situations where memory does not start at zero (due to AMP or IOMMU-less
virtualization), and thus the IMA doesn't start at zero, and thus the
device tree effective address does not equal the physical address.

Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 6c493685
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+3 −4
Original line number Diff line number Diff line
@@ -139,8 +139,7 @@ __start:
	trap
#endif /* CONFIG_PPC_PMAC */

1:	mr	r31,r3			/* save parameters */
	mr	r30,r4
1:	mr	r31,r3			/* save device tree ptr */
	li	r24,0			/* cpu # */

/*
@@ -964,8 +963,8 @@ start_here:
 * Do early platform-specific initialization,
 * and set up the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	li	r3,0
	mr	r4,r31
	bl	machine_init
	bl	__save_cpu_setup
	bl	MMU_init
+3 −12
Original line number Diff line number Diff line
@@ -58,13 +58,7 @@
_ENTRY(_stext);
_ENTRY(_start);

	/* Save parameters we are passed.
	*/
	mr	r31,r3
	mr	r30,r4
	mr	r29,r5
	mr	r28,r6
	mr	r27,r7
	mr	r31,r3			/* save device tree ptr */

	/* We have to turn on the MMU right away so we get cache modes
	 * set correctly.
@@ -849,11 +843,8 @@ start_here:
/*
 * Decide what sort of machine this is and initialize the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	li	r3,0
	mr	r4,r31
	bl	machine_init
	bl	MMU_init

+3 −13
Original line number Diff line number Diff line
@@ -61,14 +61,7 @@ _ENTRY(_start);
	 * of abatron_pteptrs
	 */
	nop
/*
 * Save parameters we are passed
 */
	mr	r31,r3
	mr	r30,r4
	mr	r29,r5
	mr	r28,r6
	mr	r27,r7
	mr	r31,r3		/* save device tree ptr */
	li	r24,0		/* CPU number */

	bl	init_cpu_state
@@ -120,11 +113,8 @@ _ENTRY(_start);
/*
 * Decide what sort of machine this is and initialize the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	li	r3,0
	mr	r4,r31
	bl	machine_init
	bl	MMU_init

+3 −10
Original line number Diff line number Diff line
@@ -76,11 +76,7 @@ _ENTRY(_start);
 */
	.globl	__start
__start:
	mr	r31,r3			/* save parameters */
	mr	r30,r4
	mr	r29,r5
	mr	r28,r6
	mr	r27,r7
	mr	r31,r3			/* save device tree ptr */

	/* We have to turn on the MMU right away so we get cache modes
	 * set correctly.
@@ -723,11 +719,8 @@ start_here:
/*
 * Decide what sort of machine this is and initialize the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	li	r3,0
	mr	r4,r31
	bl	machine_init
	bl	MMU_init

+26 −16
Original line number Diff line number Diff line
@@ -63,14 +63,27 @@ _ENTRY(_start);
	 * of abatron_pteptrs
	 */
	nop
/*
 * Save parameters we are passed
 */
	mr	r31,r3
	mr	r30,r4
	mr	r29,r5
	mr	r28,r6
	mr	r27,r7

	/* Translate device tree address to physical, save in r30/r31 */
	mfmsr	r16
	mfspr	r17,SPRN_PID
	rlwinm	r17,r17,16,0x3fff0000	/* turn PID into MAS6[SPID] */
	rlwimi	r17,r16,28,0x00000001	/* turn MSR[DS] into MAS6[SAS] */
	mtspr	SPRN_MAS6,r17

	tlbsx	0,r3			/* must succeed */

	mfspr	r16,SPRN_MAS1
	mfspr	r20,SPRN_MAS3
	rlwinm	r17,r16,25,0x1f		/* r17 = log2(page size) */
	li	r18,1024
	slw	r18,r18,r17		/* r18 = page size */
	addi	r18,r18,-1
	and	r19,r3,r18		/* r19 = page offset */
	andc	r31,r20,r18		/* r3 = page base */
	or	r31,r31,r19		/* r3 = devtree phys addr */
	mfspr	r30,SPRN_MAS7

	li	r25,0			/* phys kernel start (low) */
	li	r24,0			/* CPU number */
	li	r23,0			/* phys kernel start (high) */
@@ -198,11 +211,8 @@ _ENTRY(__early_start)
/*
 * Decide what sort of machine this is and initialize the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	mr	r3,r30
	mr	r4,r31
	bl	machine_init
	bl	MMU_init

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