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Commit 6a00a09e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: update to latest gfx8 golden register settings 



Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c61bf649

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+7 −0
Original line number Diff line number Diff line
@@ -116,11 +116,14 @@ static const u32 golden_settings_tonga_a11[] = 
	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,

	mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,

	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,

	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,

	mmTCC_CTRL, 0x00100000, 0xf31fff7f,

	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,

	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,

	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,

	mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,

	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,

};



static const u32 tonga_golden_common_all[] =
@@ -224,8 +227,10 @@ static const u32 golden_settings_iceland_a11[] = 
	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,

	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,

	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,

	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,

	mmTCC_CTRL, 0x00100000, 0xf31fff7f,

	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,

	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,

	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,

	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
@@ -318,7 +323,9 @@ static const u32 cz_golden_settings_a11[] = 
	mmGB_GPU_ID, 0x0000000f, 0x00000000,

	mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,

	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,

	mmTA_CNTL_AUX, 0x000f000f, 0x00010000,

	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,

	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,

	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302

};