arm/imx6q: add smp and cpu hotplug support

	select ARM_GIC

	select CACHE_L2X0

	select CPU_V7

	select HAVE_ARM_SCU

	select HAVE_IMX_GPC

	select HAVE_IMX_MMDC

	select HAVE_IMX_SRC

obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o

obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o

obj-$(CONFIG_HAVE_IMX_SRC) += src.o

obj-$(CONFIG_CPU_V7) += head-v7.o

AFLAGS_head-v7.o :=-Wa,-march=armv7-a

obj-$(CONFIG_SMP) += platsmp.o

obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o

obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o

/*

 * Copyright 2011 Freescale Semiconductor, Inc.

 * Copyright 2011 Linaro Ltd.

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */

#include <linux/linkage.h>

#include <linux/init.h>

#include <asm/hardware/cache-l2x0.h>

	.section ".text.head", "ax"

	__CPUINIT

/*

 * The secondary kernel init calls v7_flush_dcache_all before it enables

 * the L1; however, the L1 comes out of reset in an undefined state, so

 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch

 * of cache lines with uninitialized data and uninitialized tags to get

 * written out to memory, which does really unpleasant things to the main

 * processor.  We fix this by performing an invalidate, rather than a

 * clean + invalidate, before jumping into the kernel.

 *

 * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs

 * to be called for both secondary cores startup and primary core resume

 * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.

 */

ENTRY(v7_invalidate_l1)

	mov	r0, #0

	mcr	p15, 2, r0, c0, c0, 0

	mrc	p15, 1, r0, c0, c0, 0

	ldr	r1, =0x7fff

	and	r2, r1, r0, lsr #13

	ldr	r1, =0x3ff

	and	r3, r1, r0, lsr #3	@ NumWays - 1

	add	r2, r2, #1		@ NumSets

	and	r0, r0, #0x7

	add	r0, r0, #4	@ SetShift

	clz	r1, r3		@ WayShift

	add	r4, r3, #1	@ NumWays

1:	sub	r2, r2, #1	@ NumSets--

	mov	r3, r4		@ Temp = NumWays

2:	subs	r3, r3, #1	@ Temp--

	mov	r5, r3, lsl r1

	mov	r6, r2, lsl r0

	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)

	mcr	p15, 0, r5, c7, c6, 2

	bgt	2b

	cmp	r2, #0

	bgt	1b

	dsb

	isb

	mov	pc, lr

ENDPROC(v7_invalidate_l1)

#ifdef CONFIG_SMP

ENTRY(v7_secondary_startup)

	bl	v7_invalidate_l1

	b	secondary_startup

ENDPROC(v7_secondary_startup)

#endif

/*

 * Copyright 2011 Freescale Semiconductor, Inc.

 * Copyright 2011 Linaro Ltd.

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */

#include <linux/errno.h>

#include <asm/cacheflush.h>

#include <mach/common.h>

int platform_cpu_kill(unsigned int cpu)

{

	return 1;

}

/*

 * platform-specific code to shutdown a CPU

 *

 * Called with IRQs disabled

 */

void platform_cpu_die(unsigned int cpu)

{

	flush_cache_all();

	imx_enable_cpu(cpu, false);

	cpu_do_idle();

	/* We should never return from idle */

	panic("cpu %d unexpectedly exit from shutdown\n", cpu);

}

int platform_cpu_disable(unsigned int cpu)

{

	/*

	 * we don't allow CPU 0 to be shutdown (it is still too special

	 * e.g. clock tick interrupts)

	 */

	return cpu == 0 ? -EPERM : 0;

}

/*

 * Copyright 2011 Freescale Semiconductor, Inc.

 * Copyright 2011 Linaro Ltd.

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */

#include <linux/init.h>

#include <linux/clockchips.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <asm/smp_twd.h>

/*

 * Setup the local clock events for a CPU.

 */

int __cpuinit local_timer_setup(struct clock_event_device *evt)

{

	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");

	if (!twd_base) {

		twd_base = of_iomap(np, 0);

		WARN_ON(!twd_base);

	}

	evt->irq = irq_of_parse_and_map(np, 0);

	twd_timer_setup(evt);

	return 0;

}