Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 68055915 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86/intel/uncore: Fix boot crash on SBOX PMU on Haswell-EP 



There were several reports that on some systems writing the SBOX0 PMU
initialization MSR would #GP at boot. This did not happen on all
systems -- my two test systems booted fine.

Writing the three initialization bits bit-by-bit seems to avoid the
problem. So add a special callback to do just that.

This replaces an earlier patch that disabled the SBOX.

Reported-by: default avatarAlexei Starovoitov <alexei.starovoitov@gmail.com>
Reported-and-Tested-by: default avatarPatrick Lu <patrick.lu@intel.com>
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Link: http://lkml.kernel.org/r/1415062828-19759-4-git-send-email-andi@firstfloor.org


[ Fixed a whitespace error and added attribution tags that were left out inexplicably. ]
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 41a134a5

arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c

+30 −3
Original line number Diff line number Diff line
@@ -486,14 +486,17 @@ static struct attribute_group snbep_uncore_qpi_format_group = { 
	.attrs = snbep_uncore_qpi_formats_attr,

};



#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT()			\

	.init_box	= snbep_uncore_msr_init_box,		\

#define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT()			\

	.disable_box	= snbep_uncore_msr_disable_box,		\

	.enable_box	= snbep_uncore_msr_enable_box,		\

	.disable_event	= snbep_uncore_msr_disable_event,	\

	.enable_event	= snbep_uncore_msr_enable_event,	\

	.read_counter	= uncore_msr_read_counter



#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT()			\

	__SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),			\

	.init_box	= snbep_uncore_msr_init_box		\



static struct intel_uncore_ops snbep_uncore_msr_ops = {

	SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),

};
@@ -1919,6 +1922,30 @@ static struct intel_uncore_type hswep_uncore_cbox = { 
	.format_group		= &hswep_uncore_cbox_format_group,

};



/*

 * Write SBOX Initialization register bit by bit to avoid spurious #GPs

 */

static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box)

{

	unsigned msr = uncore_msr_box_ctl(box);



	if (msr) {

		u64 init = SNBEP_PMON_BOX_CTL_INT;

		u64 flags = 0;

		int i;



		for_each_set_bit(i, (unsigned long *)&init, 64) {

			flags |= (1ULL << i);

			wrmsrl(msr, flags);

		}

	}

}



static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = {

	__SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),

	.init_box		= hswep_uncore_sbox_msr_init_box

};



static struct attribute *hswep_uncore_sbox_formats_attr[] = {

	&format_attr_event.attr,

	&format_attr_umask.attr,
@@ -1944,7 +1971,7 @@ static struct intel_uncore_type hswep_uncore_sbox = { 
	.event_mask		= HSWEP_S_MSR_PMON_RAW_EVENT_MASK,

	.box_ctl		= HSWEP_S0_MSR_PMON_BOX_CTL,

	.msr_offset		= HSWEP_SBOX_MSR_OFFSET,

	.ops			= &snbep_uncore_msr_ops,

	.ops			= &hswep_uncore_sbox_msr_ops,

	.format_group		= &hswep_uncore_sbox_format_group,

};