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Commit 6502fbfa authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: Add support for RS880 chips 



These are new AMD IGP chips

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 90bc1a65

drivers/gpu/drm/radeon/r600_cp.c

+15 −7
Original line number Diff line number Diff line
@@ -384,8 +384,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 
		DRM_INFO("Loading RV670 PFP Microcode\n");

		for (i = 0; i < PFP_UCODE_SIZE; i++)

			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);

	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {

		DRM_INFO("Loading RS780 CP Microcode\n");

	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {

		DRM_INFO("Loading RS780/RS880 CP Microcode\n");

		for (i = 0; i < PM4_UCODE_SIZE; i++) {

			RADEON_WRITE(R600_CP_ME_RAM_DATA,

				     RS780_cp_microcode[i][0]);
@@ -396,7 +397,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 
		}



		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);

		DRM_INFO("Loading RS780 PFP Microcode\n");

		DRM_INFO("Loading RS780/RS880 PFP Microcode\n");

		for (i = 0; i < PFP_UCODE_SIZE; i++)

			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);

	}
@@ -783,6 +784,7 @@ static void r600_gfx_init(struct drm_device *dev, 
		break;

	case CHIP_RV610:

	case CHIP_RS780:

	case CHIP_RS880:

	case CHIP_RV620:

		dev_priv->r600_max_pipes = 1;

		dev_priv->r600_max_tile_pipes = 1;
@@ -917,7 +919,8 @@ static void r600_gfx_init(struct drm_device *dev, 
	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))

		RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);

	else

		RADEON_WRITE(R600_DB_DEBUG, 0);
@@ -935,7 +938,8 @@ static void r600_gfx_init(struct drm_device *dev, 
	sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);

	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {

		sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |

				    R600_FETCH_FIFO_HIWATER(0xa) |

				    R600_DONE_FIFO_HIWATER(0xe0) |
@@ -978,7 +982,8 @@ static void r600_gfx_init(struct drm_device *dev, 
					    R600_NUM_ES_STACK_ENTRIES(0));

	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {

		/* no vertex cache */

		sq_config &= ~R600_VC_ENABLE;
@@ -1035,7 +1040,8 @@ static void r600_gfx_init(struct drm_device *dev, 


	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))

		RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));

	else

		RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
@@ -1078,6 +1084,7 @@ static void r600_gfx_init(struct drm_device *dev, 
		break;

	case CHIP_RV610:

	case CHIP_RS780:

	case CHIP_RS880:

	case CHIP_RV620:

		gs_prim_buffer_depth = 32;

		break;
@@ -1123,6 +1130,7 @@ static void r600_gfx_init(struct drm_device *dev, 
	switch (dev_priv->flags & RADEON_FAMILY_MASK) {

	case CHIP_RV610:

	case CHIP_RS780:

	case CHIP_RS880:

	case CHIP_RV620:

		tc_cntl = R600_TC_L2_SIZE(8);

		break;

drivers/gpu/drm/radeon/radeon_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ enum radeon_family { 
	CHIP_RV635,

	CHIP_RV670,

	CHIP_RS780,

	CHIP_RS880,

	CHIP_RV770,

	CHIP_RV730,

	CHIP_RV710,

include/drm/drm_pciids.h

+5 −0
Original line number Diff line number Diff line
@@ -370,6 +370,11 @@ 
	{0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9711, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9713, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0x1002, 0x9714, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \

	{0, 0, 0}



#define r128_PCI_IDS \