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Commit 60687ba7 authored by RA-Shiang Tu's avatar RA-Shiang Tu Committed by John W. Linville
Browse files

rt2x00: Add support for RT5390 chip 



Add new RT5390 chip support

Signed-off-by: default avatarShiang Tu <shiang_tu@ralinktech.com>
Signed-off-by: default avatarIvo van Doorn <IvDoorn@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent fe59147c

drivers/net/wireless/rt2x00/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -97,6 +97,18 @@ config RT2800PCI_RT35XX 
	  Support for these devices is non-functional at the moment and is

	  intended for testers and developers.



config RT2800PCI_RT53XX

       bool "rt2800-pci - Include support for rt53xx devices (EXPERIMENTAL)"

       depends on EXPERIMENTAL

       default n

       ---help---

         This adds support for rt53xx wireless chipset family to the

         rt2800pci driver.

         Supported chips: RT5390



         Support for these devices is non-functional at the moment and is

         intended for testers and developers.



endif



config RT2500USB

drivers/net/wireless/rt2x00/rt2800.h

+58 −1
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)

 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)

 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)

 * RF5390 2.4G 1T1R

 */

#define RF2820				0x0001

#define RF2850				0x0002
@@ -65,6 +66,7 @@ 
#define RF3320				0x000b

#define RF3322				0x000c

#define RF3853				0x000d

#define RF5390                         0x5390



/*

 * Chipset revisions.
@@ -77,6 +79,7 @@ 
#define REV_RT3071E			0x0211

#define REV_RT3090E			0x0211

#define REV_RT3390E			0x0211

#define REV_RT5390F                    0x0502



/*

 * Signal information.
@@ -120,6 +123,13 @@ 
#define E2PROM_CSR_LOAD_STATUS		FIELD32(0x00000040)

#define E2PROM_CSR_RELOAD		FIELD32(0x00000080)



/*

 * AUX_CTRL: Aux/PCI-E related configuration

 */

#define AUX_CTRL               0x10c

#define AUX_CTRL_WAKE_PCIE_EN          FIELD32(0x00000002)

#define AUX_CTRL_FORCE_PCIE_CLK        FIELD32(0x00000400)



/*

 * OPT_14: Unknown register used by rt3xxx devices.

 */
@@ -454,7 +464,7 @@ 
 */

#define	RF_CSR_CFG			0x0500

#define RF_CSR_CFG_DATA			FIELD32(0x000000ff)

#define RF_CSR_CFG_REGNUM		FIELD32(0x00001f00)

#define RF_CSR_CFG_REGNUM              FIELD32(0x00003f00)

#define RF_CSR_CFG_WRITE		FIELD32(0x00010000)

#define RF_CSR_CFG_BUSY			FIELD32(0x00020000)
@@ -1736,6 +1746,13 @@ struct mac_iveiv_entry { 
 */

#define BBP4_TX_BF			FIELD8(0x01)

#define BBP4_BANDWIDTH			FIELD8(0x18)

#define BBP4_MAC_IF_CTRL               FIELD8(0x40)



/*

 * BBP 109

 */

#define BBP109_TX0_POWER       FIELD8(0x0f)

#define BBP109_TX1_POWER       FIELD8(0xf0)



/*

 * BBP 138: Unknown
@@ -1745,6 +1762,11 @@ struct mac_iveiv_entry { 
#define BBP138_TX_DAC1			FIELD8(0x20)

#define BBP138_TX_DAC2			FIELD8(0x40)



/*

 * BBP 152: Rx Ant

 */

#define BBP152_RX_DEFAULT_ANT  FIELD8(0x80)



/*

 * RFCSR registers

 * The wordsize of the RFCSR is 8 bits.
@@ -1754,11 +1776,17 @@ struct mac_iveiv_entry { 
 * RFCSR 1:

 */

#define RFCSR1_RF_BLOCK_EN		FIELD8(0x01)

#define RFCSR1_PLL_PD                  FIELD8(0x02)

#define RFCSR1_RX0_PD			FIELD8(0x04)

#define RFCSR1_TX0_PD			FIELD8(0x08)

#define RFCSR1_RX1_PD			FIELD8(0x10)

#define RFCSR1_TX1_PD			FIELD8(0x20)



/*

 * RFCSR 2:

 */

#define RFCSR2_RESCAL_EN               FIELD8(0x80)



/*

 * RFCSR 6:

 */
@@ -1770,6 +1798,11 @@ struct mac_iveiv_entry { 
 */

#define RFCSR7_RF_TUNING		FIELD8(0x01)



/*

 * RFCSR 11:

 */

#define RFCSR11_R                      FIELD8(0x03)



/*

 * RFCSR 12:

 */
@@ -1791,6 +1824,7 @@ struct mac_iveiv_entry { 
#define RFCSR17_TXMIXER_GAIN		FIELD8(0x07)

#define RFCSR17_TX_LO1_EN		FIELD8(0x08)

#define RFCSR17_R			FIELD8(0x20)

#define RFCSR17_CODE                   FIELD8(0x7f)



/*

 * RFCSR 20:
@@ -1823,6 +1857,9 @@ struct mac_iveiv_entry { 
/*

 * RFCSR 30:

 */

#define RFCSR30_TX_H20M                FIELD8(0x02)

#define RFCSR30_RX_H20M                FIELD8(0x04)

#define RFCSR30_RX_VCM         FIELD8(0x18)

#define RFCSR30_RF_CALIBRATION		FIELD8(0x80)



/*
@@ -1831,6 +1868,21 @@ struct mac_iveiv_entry { 
#define RFCSR31_RX_AGC_FC		FIELD8(0x1f)

#define RFCSR31_RX_H20M			FIELD8(0x20)



/*

 * RFCSR 38:

 */

#define RFCSR38_RX_LO1_EN      FIELD8(0x20)



/*

 * RFCSR 39:

 */

#define RFCSR39_RX_LO2_EN      FIELD8(0x80)



/*

 * RFCSR 49:

 */

#define RFCSR49_TX                     FIELD8(0x3f)



/*

 * RF registers

 */
@@ -1863,6 +1915,11 @@ struct mac_iveiv_entry { 
 * The wordsize of the EEPROM is 16 bits.

 */



/*

 * Chip ID

 */

#define EEPROM_CHIP_ID         0x0000



/*

 * EEPROM Version

 */

drivers/net/wireless/rt2x00/rt2800lib.c

+359 −54

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/rt2x00/rt2800pci.c

+10 −0
Original line number Diff line number Diff line
@@ -493,6 +493,13 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);

	rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);



       if (rt2x00_rt(rt2x00dev, RT5390)) {

               rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);

               rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);

               rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);

               rt2800_register_write(rt2x00dev, AUX_CTRL, reg);

       }



	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);



	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
@@ -1126,6 +1133,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { 
	{ PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },

	{ PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },

	{ PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },

#endif

#ifdef CONFIG_RT2800PCI_RT53XX

       { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) },

#endif

	{ 0, }

};

drivers/net/wireless/rt2x00/rt2x00.h

+1 −0
Original line number Diff line number Diff line
@@ -189,6 +189,7 @@ struct rt2x00_chip { 
#define RT3572		0x3572

#define RT3593		0x3593	/* PCIe */

#define RT3883		0x3883	/* WSOC */

#define RT5390         0x5390  /* 2.4GHz */



	u16 rf;

	u16 rev;