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Commit 5e5a195e authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/clock: fix missing pll type/addr when matching default entry 



This issue is a regression from 70790f4f,
and causes us to miss a special-case for C51 (NV4E) chipsets and return
the wrong reference frequency for the VPLLs.

Should fix fdo#56202

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2c25b739

drivers/gpu/drm/nouveau/core/subdev/bios/pll.c

+4 −6
Original line number Diff line number Diff line
@@ -157,11 +157,10 @@ pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) 
	while (map->reg) {

		if (map->reg == reg && *ver >= 0x20) {

			u16 addr = (data += hdr);

			while (cnt--) {

				if (nv_ro32(bios, data) == map->reg) {

			*type = map->type;

			while (cnt--) {

				if (nv_ro32(bios, data) == map->reg)

					return data;

				}

				data += *len;

			}

			return addr;
@@ -200,11 +199,10 @@ pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) 
	while (map->reg) {

		if (map->type == type && *ver >= 0x20) {

			u16 addr = (data += hdr);

			while (cnt--) {

				if (nv_ro32(bios, data) == map->reg) {

			*reg = map->reg;

			while (cnt--) {

				if (nv_ro32(bios, data) == map->reg)

					return data;

				}

				data += *len;

			}

			return addr;