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Commit 5e512d07 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull arm soc-specific updates from Arnd Bergmann:
 "This is stuff that does not fit well into another category and in
  particular is not related to a particular board.  The largest part in
  here is extending the am33xx support in the omap platform."

Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile}

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits)
  ARM: LPC32xx: Add PWM support
  ARM: LPC32xx: Add PWM clock
  ARM: LPC32xx: Set system serial based on cpu unique id
  ARM: vexpress: Config option for early printk console
  ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile
  ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses
  ARM: vexpress: Add fixed regulator for SMSC
  ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files
  ARM: vexpress: Initial common clock support
  ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
  ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
  ARM: EXYNOS: Make combiner_init function static
  ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
  ARM: versatile: Make plat-versatile clock optional
  ARM: vexpress: Check master site in daughterboard's sysctl operations
  ARM: vexpress: remove automatic errata workaround selection
  ARM: LPC32xx: Adjust to pl08x DMA interface changes
  ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
  ARM: imx: fix mx51 ehci setup errors
  ARM: imx: make ehci power/oc polarities configurable
  ...
parents 451ce7f9 233de298

arch/arm/Kconfig

+7 −4
Original line number Diff line number Diff line
@@ -260,6 +260,7 @@ config ARCH_INTEGRATOR 
	select ICST

	select GENERIC_CLOCKEVENTS

	select PLAT_VERSATILE

	select PLAT_VERSATILE_CLOCK

	select PLAT_VERSATILE_FPGA_IRQ

	select NEED_MACH_IO_H

	select NEED_MACH_MEMORY_H
@@ -277,6 +278,7 @@ config ARCH_REALVIEW 
	select GENERIC_CLOCKEVENTS

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select PLAT_VERSATILE

	select PLAT_VERSATILE_CLOCK

	select PLAT_VERSATILE_CLCD

	select ARM_TIMER_SP804

	select GPIO_PL061 if GPIOLIB
@@ -295,6 +297,7 @@ config ARCH_VERSATILE 
	select ARCH_WANT_OPTIONAL_GPIOLIB

	select NEED_MACH_IO_H if PCI

	select PLAT_VERSATILE

	select PLAT_VERSATILE_CLOCK

	select PLAT_VERSATILE_CLCD

	select PLAT_VERSATILE_FPGA_IRQ

	select ARM_TIMER_SP804
@@ -307,7 +310,7 @@ config ARCH_VEXPRESS 
	select ARM_AMBA

	select ARM_TIMER_SP804

	select CLKDEV_LOOKUP

	select HAVE_MACH_CLKDEV

	select COMMON_CLK

	select GENERIC_CLOCKEVENTS

	select HAVE_CLK

	select HAVE_PATA_PLATFORM
@@ -315,6 +318,7 @@ config ARCH_VEXPRESS 
	select NO_IOPORT

	select PLAT_VERSATILE

	select PLAT_VERSATILE_CLCD

	select REGULATOR_FIXED_VOLTAGE if REGULATOR

	help

	  This enables support for the ARM Ltd Versatile Express boards.
@@ -567,6 +571,7 @@ config ARCH_LPC32XX 
	select CLKDEV_LOOKUP

	select GENERIC_CLOCKEVENTS

	select USE_OF

	select HAVE_PWM

	help

	  Support for the NXP LPC32XX family of processors
@@ -913,7 +918,7 @@ config ARCH_NOMADIK 
	select ARM_AMBA

	select ARM_VIC

	select CPU_ARM926T

	select CLKDEV_LOOKUP

	select COMMON_CLK

	select GENERIC_CLOCKEVENTS

	select PINCTRL

	select MIGHT_HAVE_CACHE_L2X0
@@ -1022,8 +1027,6 @@ source "arch/arm/mach-kirkwood/Kconfig" 


source "arch/arm/mach-ks8695/Kconfig"



source "arch/arm/mach-lpc32xx/Kconfig"



source "arch/arm/mach-msm/Kconfig"



source "arch/arm/mach-mv78xx0/Kconfig"

arch/arm/Kconfig.debug

+26 −0
Original line number Diff line number Diff line
@@ -310,6 +310,32 @@ choice 
		  The uncompressor code port configuration is now handled

		  by CONFIG_S3C_LOWLEVEL_UART_PORT.



	config DEBUG_VEXPRESS_UART0_DETECT

		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"

		depends on ARCH_VEXPRESS && CPU_CP15_MMU

		help

		  This option enables a simple heuristic which tries to determine

		  the motherboard's memory map variant (original or RS1) and then

		  choose the relevant UART0 base address.



		  Note that this will only work with standard A-class core tiles,

		  and may fail with non-standard SMM or custom software models.



	config DEBUG_VEXPRESS_UART0_CA9

		bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"

		depends on ARCH_VEXPRESS

		help

		  This option selects UART0 at 0x10009000. Except for custom models,

		  this applies only to the V2P-CA9 tile.



	config DEBUG_VEXPRESS_UART0_RS1

		bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"

		depends on ARCH_VEXPRESS

		help

		  This option selects UART0 at 0x1c090000. This applies to most

		  of the tiles using the RS1 memory map, including all new A-class

		  core tiles, FPGA-based SMMs and software models.



	config DEBUG_LL_UART_NONE

		bool "No low-level debugging UART"

		help

arch/arm/boot/dts/ea3250.dts

0 → 100644
+157 −0
Original line number Diff line number Diff line 
/*

 * Embedded Artists LPC3250 board

 *

 * Copyright 2012 Roland Stigge <stigge@antcom.de>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/dts-v1/;

/include/ "lpc32xx.dtsi"



/ {

	model = "Embedded Artists LPC3250 board based on NXP LPC3250";

	compatible = "ea,ea3250", "nxp,lpc3250";

	#address-cells = <1>;

	#size-cells = <1>;



	memory {

		device_type = "memory";

		reg = <0 0x4000000>;

	};



	ahb {

		mac: ethernet@31060000 {

			phy-mode = "rmii";

			use-iram;

		};



		/* Here, choose exactly one from: ohci, usbd */

		ohci@31020000 {

			transceiver = <&isp1301>;

			status = "okay";

		};



/*

		usbd@31020000 {

			transceiver = <&isp1301>;

			status = "okay";

		};

*/



		/* 128MB Flash via SLC NAND controller */

		slc: flash@20020000 {

			status = "okay";

			#address-cells = <1>;

			#size-cells = <1>;



			nxp,wdr-clks = <14>;

			nxp,wwidth = <260000000>;

			nxp,whold = <104000000>;

			nxp,wsetup = <200000000>;

			nxp,rdr-clks = <14>;

			nxp,rwidth = <34666666>;

			nxp,rhold = <104000000>;

			nxp,rsetup = <200000000>;

			nand-on-flash-bbt;

			gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */



			mtd0@00000000 {

				label = "ea3250-boot";

				reg = <0x00000000 0x00080000>;

				read-only;

			};



			mtd1@00080000 {

				label = "ea3250-uboot";

				reg = <0x00080000 0x000c0000>;

				read-only;

			};



			mtd2@00140000 {

				label = "ea3250-kernel";

				reg = <0x00140000 0x00400000>;

			};



			mtd3@00540000 {

				label = "ea3250-rootfs";

				reg = <0x00540000 0x07ac0000>;

			};

		};



		apb {

			uart5: serial@40090000 {

				status = "okay";

			};



			uart3: serial@40080000 {

				status = "okay";

			};



			uart6: serial@40098000 {

				status = "okay";

			};



			i2c1: i2c@400A0000 {

				clock-frequency = <100000>;



				eeprom@50 {

					compatible = "at,24c256";

					reg = <0x50>;

				};



				eeprom@57 {

					compatible = "at,24c64";

					reg = <0x57>;

				};



				uda1380: uda1380@18 {

					compatible = "nxp,uda1380";

					reg = <0x18>;

					power-gpio = <&gpio 0x59 0>;

					reset-gpio = <&gpio 0x51 0>;

					dac-clk = "wspll";

				};



				pca9532: pca9532@60 {

					compatible = "nxp,pca9532";

					gpio-controller;

					#gpio-cells = <2>;

					reg = <0x60>;

				};

			};



			i2c2: i2c@400A8000 {

				clock-frequency = <100000>;

			};



			i2cusb: i2c@31020300 {

				clock-frequency = <100000>;



				isp1301: usb-transceiver@2d {

					compatible = "nxp,isp1301";

					reg = <0x2d>;

				};

			};



			sd@20098000 {

				wp-gpios = <&pca9532 5 0>;

				cd-gpios = <&pca9532 4 0>;

				cd-inverted;

				bus-width = <4>;

				status = "okay";

			};

		};



		fab {

			uart1: serial@40014000 {

				status = "okay";

			};

		};

	};

};

arch/arm/boot/dts/lpc32xx.dtsi

+51 −23
Original line number Diff line number Diff line
@@ -35,13 +35,14 @@ 
		slc: flash@20020000 {

			compatible = "nxp,lpc3220-slc";

			reg = <0x20020000 0x1000>;

			status = "disable";

			status = "disabled";

		};



		mlc: flash@200B0000 {

		mlc: flash@200a8000 {

			compatible = "nxp,lpc3220-mlc";

			reg = <0x200B0000 0x1000>;

			status = "disable";

			reg = <0x200a8000 0x11000>;

			interrupts = <11 0>;

			status = "disabled";

		};



		dma@31000000 {
@@ -57,21 +58,21 @@ 
			compatible = "nxp,ohci-nxp", "usb-ohci";

			reg = <0x31020000 0x300>;

			interrupts = <0x3b 0>;

			status = "disable";

			status = "disabled";

		};



		usbd@31020000 {

			compatible = "nxp,lpc3220-udc";

			reg = <0x31020000 0x300>;

			interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;

			status = "disable";

			status = "disabled";

		};



		clcd@31040000 {

			compatible = "arm,pl110", "arm,primecell";

			reg = <0x31040000 0x1000>;

			interrupts = <0x0e 0>;

			status = "disable";

			status = "disabled";

		};



		mac: ethernet@31060000 {
@@ -114,9 +115,10 @@ 
			};



			sd@20098000 {

				compatible = "arm,pl180", "arm,primecell";

				compatible = "arm,pl18x", "arm,primecell";

				reg = <0x20098000 0x1000>;

				interrupts = <0x0f 0>, <0x0d 0>;

				status = "disabled";

			};



			i2s1: i2s@2009C000 {
@@ -124,24 +126,42 @@ 
				reg = <0x2009C000 0x1000>;

			};



			/* UART5 first since it is the default console, ttyS0 */

			uart5: serial@40090000 {

				/* actually, ns16550a w/ 64 byte fifos! */

				compatible = "nxp,lpc3220-uart";

				reg = <0x40090000 0x1000>;

				interrupts = <9 0>;

				clock-frequency = <13000000>;

				reg-shift = <2>;

				status = "disabled";

			};



			uart3: serial@40080000 {

				compatible = "nxp,serial";

				compatible = "nxp,lpc3220-uart";

				reg = <0x40080000 0x1000>;

				interrupts = <7 0>;

				clock-frequency = <13000000>;

				reg-shift = <2>;

				status = "disabled";

			};



			uart4: serial@40088000 {

				compatible = "nxp,serial";

				compatible = "nxp,lpc3220-uart";

				reg = <0x40088000 0x1000>;

			};



			uart5: serial@40090000 {

				compatible = "nxp,serial";

				reg = <0x40090000 0x1000>;

				interrupts = <8 0>;

				clock-frequency = <13000000>;

				reg-shift = <2>;

				status = "disabled";

			};



			uart6: serial@40098000 {

				compatible = "nxp,serial";

				compatible = "nxp,lpc3220-uart";

				reg = <0x40098000 0x1000>;

				interrupts = <10 0>;

				clock-frequency = <13000000>;

				reg-shift = <2>;

				status = "disabled";

			};



			i2c1: i2c@400A0000 {
@@ -192,18 +212,24 @@ 
			};



			uart1: serial@40014000 {

				compatible = "nxp,serial";

				compatible = "nxp,lpc3220-hsuart";

				reg = <0x40014000 0x1000>;

				interrupts = <26 0>;

				status = "disabled";

			};



			uart2: serial@40018000 {

				compatible = "nxp,serial";

				compatible = "nxp,lpc3220-hsuart";

				reg = <0x40018000 0x1000>;

				interrupts = <25 0>;

				status = "disabled";

			};



			uart7: serial@4001C000 {

				compatible = "nxp,serial";

				reg = <0x4001C000 0x1000>;

			uart7: serial@4001c000 {

				compatible = "nxp,lpc3220-hsuart";

				reg = <0x4001c000 0x1000>;

				interrupts = <24 0>;

				status = "disabled";

			};



			rtc@40024000 {
@@ -235,19 +261,21 @@ 
				compatible = "nxp,lpc3220-adc";

				reg = <0x40048000 0x1000>;

				interrupts = <0x27 0>;

				status = "disable";

				status = "disabled";

			};



			tsc@40048000 {

				compatible = "nxp,lpc3220-tsc";

				reg = <0x40048000 0x1000>;

				interrupts = <0x27 0>;

				status = "disable";

				status = "disabled";

			};



			key@40050000 {

				compatible = "nxp,lpc3220-key";

				reg = <0x40050000 0x1000>;

				interrupts = <54 0>;

				status = "disabled";

			};



		};

arch/arm/boot/dts/phy3250.dts

+61 −0
Original line number Diff line number Diff line
@@ -54,6 +54,17 @@ 
			#address-cells = <1>;

			#size-cells = <1>;



			nxp,wdr-clks = <14>;

			nxp,wwidth = <40000000>;

			nxp,whold = <100000000>;

			nxp,wsetup = <100000000>;

			nxp,rdr-clks = <14>;

			nxp,rwidth = <40000000>;

			nxp,rhold = <66666666>;

			nxp,rsetup = <100000000>;

			nand-on-flash-bbt;

			gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */



			mtd0@00000000 {

				label = "phy3250-boot";

				reg = <0x00000000 0x00064000>;
@@ -83,6 +94,14 @@ 
		};



		apb {

			uart5: serial@40090000 {

				status = "okay";

			};



			uart3: serial@40080000 {

				status = "okay";

			};



			i2c1: i2c@400A0000 {

				clock-frequency = <100000>;
@@ -114,16 +133,58 @@ 
			};



			ssp0: ssp@20084000 {

				#address-cells = <1>;

				#size-cells = <0>;

				pl022,num-chipselects = <1>;

				cs-gpios = <&gpio 3 5 0>;



				eeprom: at25@0 {

					pl022,hierarchy = <0>;

					pl022,interface = <0>;

					pl022,slave-tx-disable = <0>;

					pl022,com-mode = <0>;

					pl022,rx-level-trig = <1>;

					pl022,tx-level-trig = <1>;

					pl022,ctrl-len = <11>;

					pl022,wait-state = <0>;

					pl022,duplex = <0>;



					at25,byte-len = <0x8000>;

					at25,addr-mode = <2>;

					at25,page-size = <64>;



					compatible = "atmel,at25";

					reg = <0>;

					spi-max-frequency = <5000000>;

				};

			};



			sd@20098000 {

				wp-gpios = <&gpio 3 0 0>;

				cd-gpios = <&gpio 3 1 0>;

				cd-inverted;

				bus-width = <4>;

				status = "okay";

			};

		};



		fab {

			uart2: serial@40018000 {

				status = "okay";

			};



			tsc@40048000 {

				status = "okay";

			};



			key@40050000 {

				status = "okay";

				keypad,num-rows = <1>;

				keypad,num-columns = <1>;

				nxp,debounce-delay-ms = <3>;

				nxp,scan-delay-ms = <34>;

				linux,keymap = <0x00000002>;

			};

		};

	};