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Commit 5c0e0088 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'davinci-v3.6-dt' of git://gitorious.org/linux-davinci/linux-davinci into next/dt 

From Sekhar Nori <nsekhar@ti.com>:
DaVinci DT support

Add DT support for DaVinci cp_intc interrupt controller

* tag 'davinci-v3.6-dt' of git://gitorious.org/linux-davinci/linux-davinci

:
  ARM: davinci: cp_intc: Add OF support for TI interrupt controller
  ARM: davinci: add runtime PM support for clock management
  ARM: davinci: cp_intc: Add irq domain support

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e3b897c1 961e657f

Documentation/devicetree/bindings/arm/davinci/cp-intc.txt

0 → 100644
+27 −0
Original line number Diff line number Diff line 
* TI Common Platform Interrupt Controller



Common Platform Interrupt Controller (cp_intc) is used on

OMAP-L1x SoCs and can support several configurable number

of interrupts.



Main node required properties:



- compatible : should be:

	"ti,cp-intc"

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The type shall be a <u32> and the value shall be 1.



  The cell contains the interrupt number in the range [0-128].

- ti,intc-size: Number of interrupts handled by the interrupt controller.

- reg: physical base address and size of the intc registers map.



Example:



	intc: interrupt-controller@1 {

		compatible = "ti,cp-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		ti,intc-size = <101>;

		reg = <0xfffee000 0x2000>;

	};

arch/arm/mach-davinci/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ config AINTC 
	bool



config CP_INTC

	select IRQ_DOMAIN

	bool



config ARCH_DAVINCI_DMx

arch/arm/mach-davinci/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -39,3 +39,4 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o 
obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o

obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o

obj-$(CONFIG_SUSPEND)			+= pm.o sleep.o

obj-$(CONFIG_HAVE_CLK)			+= pm_domain.o

arch/arm/mach-davinci/cp_intc.c

+60 −15
Original line number Diff line number Diff line
@@ -9,9 +9,14 @@ 
 * kind, whether express or implied.

 */



#include <linux/export.h>

#include <linux/init.h>

#include <linux/irq.h>

#include <linux/irqdomain.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>



#include <mach/common.h>

#include <mach/cp_intc.h>
@@ -28,7 +33,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset) 


static void cp_intc_ack_irq(struct irq_data *d)

{

	cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);

	cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);

}



/* Disable interrupt */
@@ -36,20 +41,20 @@ static void cp_intc_mask_irq(struct irq_data *d) 
{

	/* XXX don't know why we need to disable nIRQ here... */

	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);

	cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);

	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);

	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);

}



/* Enable interrupt */

static void cp_intc_unmask_irq(struct irq_data *d)

{

	cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);

	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);

}



static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)

{

	unsigned reg		= BIT_WORD(d->irq);

	unsigned mask		= BIT_MASK(d->irq);

	unsigned reg		= BIT_WORD(d->hwirq);

	unsigned mask		= BIT_MASK(d->hwirq);

	unsigned polarity	= cp_intc_read(CP_INTC_SYS_POLARITY(reg));

	unsigned type		= cp_intc_read(CP_INTC_SYS_TYPE(reg));
@@ -99,18 +104,43 @@ static struct irq_chip cp_intc_irq_chip = { 
	.irq_set_wake	= cp_intc_set_wake,

};



void __init cp_intc_init(void)

static struct irq_domain *cp_intc_domain;



static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,

			  irq_hw_number_t hw)

{

	unsigned long num_irq	= davinci_soc_info.intc_irq_num;

	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);



	irq_set_chip(virq, &cp_intc_irq_chip);

	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);

	irq_set_handler(virq, handle_edge_irq);

	return 0;

}



static const struct irq_domain_ops cp_intc_host_ops = {

	.map = cp_intc_host_map,

	.xlate = irq_domain_xlate_onetwocell,

};



int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)

{

	u32 num_irq		= davinci_soc_info.intc_irq_num;

	u8 *irq_prio		= davinci_soc_info.intc_irq_prios;

	u32 *host_map		= davinci_soc_info.intc_host_map;

	unsigned num_reg	= BITS_TO_LONGS(num_irq);

	int i;

	int i, irq_base;



	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;

	if (node) {

		davinci_intc_base = of_iomap(node, 0);

		if (of_property_read_u32(node, "ti,intc-size", &num_irq))

			pr_warn("unable to get intc-size, default to %d\n",

				num_irq);

	} else {

		davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);

	}

	if (WARN_ON(!davinci_intc_base))

		return;

		return -EINVAL;



	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
@@ -165,13 +195,28 @@ void __init cp_intc_init(void) 
		for (i = 0; host_map[i] != -1; i++)

			cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));



	/* Set up genirq dispatching for cp_intc */

	for (i = 0; i < num_irq; i++) {

		irq_set_chip(i, &cp_intc_irq_chip);

		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);

		irq_set_handler(i, handle_edge_irq);

	irq_base = irq_alloc_descs(-1, 0, num_irq, 0);

	if (irq_base < 0) {

		pr_warn("Couldn't allocate IRQ numbers\n");

		irq_base = 0;

	}



	/* create a legacy host */

	cp_intc_domain = irq_domain_add_legacy(node, num_irq,

					irq_base, 0, &cp_intc_host_ops, NULL);



	if (!cp_intc_domain) {

		pr_err("cp_intc: failed to allocate irq host!\n");

		return -EINVAL;

	}



	/* Enable global interrupt */

	cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);



	return 0;

}



void __init cp_intc_init(void)

{

	cp_intc_of_init(NULL, NULL);

}

arch/arm/mach-davinci/include/mach/cp_intc.h

+1 −0
Original line number Diff line number Diff line
@@ -52,5 +52,6 @@ 
#define CP_INTC_VECTOR_ADDR(n)		(0x2000 + (n << 2))



void __init cp_intc_init(void);

int __init cp_intc_of_init(struct device_node *, struct device_node *);



#endif	/* __ASM_HARDWARE_CP_INTC_H */