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Commit 5b5896e4 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: enable lvds pin pairs before dpll on gen2 



Otherwise things migt not work too well.

Breakage introduced in

commit eb1cbe48
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Mar 28 23:12:16 2012 +0200

    drm/i915: split PLL update code out of i9xx_crtc_mode_set

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@vger.kernel.org (for 3.5 only)
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5698bd75

drivers/gpu/drm/i915/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -4191,12 +4191,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc, 
	POSTING_READ(DPLL(pipe));

	udelay(150);



	I915_WRITE(DPLL(pipe), dpll);



	/* Wait for the clocks to stabilize. */

	POSTING_READ(DPLL(pipe));

	udelay(150);



	/* The LVDS pin pair needs to be on before the DPLLs are enabled.

	 * This is an exception to the general rule that mode_set doesn't turn

	 * things on.
@@ -4204,6 +4198,12 @@ static void i8xx_update_pll(struct drm_crtc *crtc, 
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

		intel_update_lvds(crtc, clock, adjusted_mode);



	I915_WRITE(DPLL(pipe), dpll);



	/* Wait for the clocks to stabilize. */

	POSTING_READ(DPLL(pipe));

	udelay(150);



	/* The pixel multiplier can only be updated once the

	 * DPLL is enabled and the clocks are stable.

	 *