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Commit 594a9dfa authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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[BNX2]: Add write posting comment. 



Add comment to explain why we cannot read back after chip reset
before delaying.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8e545881

drivers/net/bnx2.c

+4 −0
Original line number Diff line number Diff line
@@ -3934,6 +3934,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) 
		/* Chip reset. */

		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);



		/* Reading back any register after chip reset will hang the

		 * bus on 5706 A0 and A1.  The msleep below provides plenty

		 * of margin for write posting.

		 */

		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||

		    (CHIP_ID(bp) == CHIP_ID_5706_A1))

			msleep(20);