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Commit 55d8a653 authored by Paul Walmsley's avatar Paul Walmsley Committed by paul
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OMAP2/3: move SDRC macros to mach-omap2/sdrc.h 



clock34xx.c contains some macros which probably belong in mach-omap2/sdrc.h.
Move those macros to mach-omap2/sdrc.h.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 06b16939

arch/arm/mach-omap2/clock34xx.c

+0 −14
Original line number Diff line number Diff line
@@ -322,22 +322,8 @@ static struct omap_clk omap34xx_clks[] = { 


#define MAX_DPLL_WAIT_TRIES		1000000



#define MIN_SDRC_DLL_LOCK_FREQ		83000000



#define CYCLES_PER_MHZ			1000000



/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */

#define SDRC_MPURATE_SCALE		8



/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */

#define SDRC_MPURATE_BASE_SHIFT		9



/*

 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at

 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize

 */

#define SDRC_MPURATE_LOOPS		96



/*

 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks

 * that are sourced by DPLL5, and both of these require this clock

arch/arm/mach-omap2/sdrc.h

+16 −0
Original line number Diff line number Diff line
@@ -56,4 +56,20 @@ static inline u32 sms_read_reg(u16 reg) 
			OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))

#endif	/* __ASSEMBLER__ */



/* Minimum frequency that the SDRC DLL can lock at */

#define MIN_SDRC_DLL_LOCK_FREQ		83000000



/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */

#define SDRC_MPURATE_SCALE		8



/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */

#define SDRC_MPURATE_BASE_SHIFT		9



/*

 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at

 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize

 */

#define SDRC_MPURATE_LOOPS		96





#endif