Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 541b03ad authored by Nicolin Chen's avatar Nicolin Chen Committed by Mark Brown
Browse files

ASoC: fsl_ssi: Fix the incorrect limitation of the bit clock rate 



According to i.MX Reference Manual, the bit-clock frequency generated
by SSI must be never greater than 1/5 of the peripheral clock frequency.

This peripheral clock, however, is not baudclk but the IPG clock (i.e.
ssi_private->clk in the fsl_ssi driver).

So this patch just simply fixes the incorrect limitation applied to
the bit clock (baudclk) rate.

Signed-off-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent bfa76d49

sound/soc/fsl/fsl_ssi.c

+7 −4
Original line number Diff line number Diff line
@@ -603,10 +603,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 
	factor = (div2 + 1) * (7 * psr + 1) * 2;



	for (i = 0; i < 255; i++) {

		/* The bclk rate must be smaller than 1/5 sysclk rate */

		if (factor * (i + 1) < 5)

			continue;



		tmprate = freq * factor * (i + 2);



		if (baudclk_is_used)
@@ -614,6 +610,13 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 
		else

			clkrate = clk_round_rate(ssi_private->baudclk, tmprate);



		/*

		 * Hardware limitation: The bclk rate must be

		 * never greater than 1/5 IPG clock rate

		 */

		if (clkrate * 5 > clk_get_rate(ssi_private->clk))

			continue;



		clkrate /= factor;

		afreq = clkrate / (i + 1);