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Commit 5210436b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-clock-fixes-for-v3.18' of... 

Merge tag 'renesas-clock-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes

Pull "Renesas ARM Based SoC Clock Fixes for v3.18" from Simon Horman:

* Correct IIC0 parent clock for r8a7740
* Add missing INTCA clock for irqpin module for r8a7740
* Correct SD3CKCR address on r8a7790

* tag 'renesas-clock-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock
  ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module
  ARM: shmobile: r8a7790: Fix SD3CKCR address

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3410d424 4f37828d

arch/arm/mach-shmobile/clock-r8a7740.c

+7 −2
Original line number Diff line number Diff line
@@ -455,7 +455,7 @@ enum { 
	MSTP128, MSTP127, MSTP125,

	MSTP116, MSTP111, MSTP100, MSTP117,



	MSTP230,

	MSTP230, MSTP229,

	MSTP222,

	MSTP218, MSTP217, MSTP216, MSTP214,

	MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -474,11 +474,12 @@ static struct clk mstp_clks[MSTP_NR] = { 
	[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S],	SMSTPCR1, 27, 0), /* CEU20 */

	[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR1, 25, 0), /* TMU0 */

	[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	SMSTPCR1, 17, 0), /* LCDC1 */

	[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR1, 16, 0), /* IIC0 */

	[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP],	SMSTPCR1, 16, 0), /* IIC0 */

	[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR1, 11, 0), /* TMU1 */

	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	SMSTPCR1,  0, 0), /* LCDC0 */



	[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR2, 30, 0), /* SCIFA6 */

	[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR2, 29, 0), /* INTCA */

	[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR2, 22, 0), /* SCIFA7 */

	[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 18, 0), /* DMAC1 */

	[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 17, 0), /* DMAC2 */
@@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("sh-dma-engine.0",	&mstp_clks[MSTP218]),

	CLKDEV_DEV_ID("sh-sci.7",		&mstp_clks[MSTP222]),

	CLKDEV_DEV_ID("e6cd0000.serial",	&mstp_clks[MSTP222]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.0",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.1",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.2",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.3",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("sh-sci.6",		&mstp_clks[MSTP230]),

	CLKDEV_DEV_ID("e6cc0000.serial",	&mstp_clks[MSTP230]),

arch/arm/mach-shmobile/clock-r8a7790.c

+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ 


#define SDCKCR		0xE6150074

#define SD2CKCR		0xE6150078

#define SD3CKCR		0xE615007C

#define SD3CKCR		0xE615026C

#define MMC0CKCR	0xE6150240

#define MMC1CKCR	0xE6150244

#define SSPCKCR		0xE6150248