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Commit 500a0e56 authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace 



When we build with ftrace enabled its possible that loadcam_entry would
have used the stack pointer (even though the code doesn't need it).  We
call loadcam_entry in __secondary_start before the stack is setup.  To
ensure that loadcam_entry doesn't use the stack pointer the easiest
solution is to just have it in asm code.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent fa6bd996

arch/powerpc/kernel/asm-offsets.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -447,6 +447,14 @@ int main(void) 
	DEFINE(PGD_T_LOG2, PGD_T_LOG2);

	DEFINE(PGD_T_LOG2, PGD_T_LOG2);

	DEFINE(PTE_T_LOG2, PTE_T_LOG2);

	DEFINE(PTE_T_LOG2, PTE_T_LOG2);

#endif

#endif

#ifdef CONFIG_FSL_BOOKE

	DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));

	DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));

	DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));

	DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));

	DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));

	DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));

#endif





#ifdef CONFIG_KVM_EXIT_TIMING

#ifdef CONFIG_KVM_EXIT_TIMING

	DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,

	DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,

arch/powerpc/mm/fsl_booke_mmu.c

+3 −22
Original line number Original line Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * Modifications by Kumar Gala (galak@kernel.crashing.org) to support

 * Modifications by Kumar Gala (galak@kernel.crashing.org) to support

 * E500 Book E processors.

 * E500 Book E processors.

 *

 *

 * Copyright 2004 Freescale Semiconductor, Inc

 * Copyright 2004,2010 Freescale Semiconductor, Inc.

 *

 *

 * This file contains the routines for initializing the MMU

 * This file contains the routines for initializing the MMU

 * on the 4xx series of chips.

 * on the 4xx series of chips.
@@ -56,19 +56,13 @@ 




unsigned int tlbcam_index;

unsigned int tlbcam_index;





#define NUM_TLBCAMS	(64)





#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)

#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)

#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"

#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"

#endif

#endif





struct tlbcam {

#define NUM_TLBCAMS	(64)

	u32	MAS0;

struct tlbcam TLBCAM[NUM_TLBCAMS];

	u32	MAS1;

	unsigned long	MAS2;

	u32	MAS3;

	u32	MAS7;

} TLBCAM[NUM_TLBCAMS];





struct tlbcamrange {

struct tlbcamrange {

	unsigned long start;

	unsigned long start;
@@ -109,19 +103,6 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa) 
	return 0;

	return 0;

}

}





void loadcam_entry(int idx)

{

	mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);

	mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);

	mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);

	mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);



	if (mmu_has_feature(MMU_FTR_BIG_PHYS))

		mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);



	asm volatile("isync;tlbwe;isync" : : : "memory");

}



/*

/*

 * Set up one of the I/D BAT (block address translation) register pairs.

 * Set up one of the I/D BAT (block address translation) register pairs.

 * The parameters are not checked; in particular size must be a power

 * The parameters are not checked; in particular size must be a power

arch/powerpc/mm/mmu_decl.h

+9 −1
Original line number Original line Diff line number Diff line
@@ -149,7 +149,15 @@ extern unsigned long mmu_mapin_ram(unsigned long top); 
extern void MMU_init_hw(void);

extern void MMU_init_hw(void);

extern unsigned long mmu_mapin_ram(unsigned long top);

extern unsigned long mmu_mapin_ram(unsigned long top);

extern void adjust_total_lowmem(void);

extern void adjust_total_lowmem(void);



extern void loadcam_entry(unsigned int index);



struct tlbcam {

	u32	MAS0;

	u32	MAS1;

	unsigned long	MAS2;

	u32	MAS3;

	u32	MAS7;

};

#elif defined(CONFIG_PPC32)

#elif defined(CONFIG_PPC32)

/* anything 32-bit except 4xx or 8xx */

/* anything 32-bit except 4xx or 8xx */

extern void MMU_init_hw(void);

extern void MMU_init_hw(void);

arch/powerpc/mm/tlb_nohash_low.S

+28 −0
Original line number Original line Diff line number Diff line
@@ -271,3 +271,31 @@ _GLOBAL(set_context) 
#else

#else

#error Unsupported processor type !

#error Unsupported processor type !

#endif

#endif



#if defined(CONFIG_FSL_BOOKE)

/*

 * extern void loadcam_entry(unsigned int index)

 *

 * Load TLBCAM[index] entry in to the L2 CAM MMU

 */

_GLOBAL(loadcam_entry)

	LOAD_REG_ADDR(r4, TLBCAM)

	mulli	r5,r3,TLBCAM_SIZE

	add	r3,r5,r4

	lwz	r4,TLBCAM_MAS0(r3)

	mtspr	SPRN_MAS0,r4

	lwz	r4,TLBCAM_MAS1(r3)

	mtspr	SPRN_MAS1,r4

	PPC_LL	r4,TLBCAM_MAS2(r3)

	mtspr	SPRN_MAS2,r4

	lwz	r4,TLBCAM_MAS3(r3)

	mtspr	SPRN_MAS3,r4

BEGIN_MMU_FTR_SECTION

	lwz	r4,TLBCAM_MAS7(r3)

	mtspr	SPRN_MAS7,r4

END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)

	isync

	tlbwe

	isync

	blr

#endif