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Commit 4f4f85fa authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Implement memory-controller clock 



The memory controller clock runs either at half or the same frequency as
the EMC clock.

Reviewed-By: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 7f06dd61

drivers/clk/tegra/clk-divider.c

+13 −0
Original line number Diff line number Diff line
@@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name, 


	return clk;

}



static const struct clk_div_table mc_div_table[] = {

	{ .val = 0, .div = 2 },

	{ .val = 1, .div = 1 },

	{ .val = 0, .div = 0 },

};



struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,

				  void __iomem *reg, spinlock_t *lock)

{

	return clk_register_divider_table(NULL, name, parent_name, 0, reg,

					  16, 1, 0, mc_div_table, lock);

}

drivers/clk/tegra/clk-tegra114.c

+6 −1
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ static DEFINE_SPINLOCK(pll_d_lock); 
static DEFINE_SPINLOCK(pll_d2_lock);

static DEFINE_SPINLOCK(pll_u_lock);

static DEFINE_SPINLOCK(pll_re_lock);

static DEFINE_SPINLOCK(emc_lock);



static struct div_nmp pllxc_nmp = {

	.divm_shift = 0,
@@ -1228,7 +1229,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, 
			       ARRAY_SIZE(mux_pllmcp_clkm),

			       CLK_SET_RATE_NO_REPARENT,

			       clk_base + CLK_SOURCE_EMC,

			       29, 3, 0, NULL);

			       29, 3, 0, &emc_lock);



	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

				    &emc_lock);

	clks[TEGRA114_CLK_MC] = clk;



	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {

		data = &tegra_periph_clk_list[i];

drivers/clk/tegra/clk-tegra124.c

+6 −1
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock); 
static DEFINE_SPINLOCK(pll_e_lock);

static DEFINE_SPINLOCK(pll_re_lock);

static DEFINE_SPINLOCK(pll_u_lock);

static DEFINE_SPINLOCK(emc_lock);



/* possible OSC frequencies in Hz */

static unsigned long tegra124_input_freq[] = {
@@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, 
	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,

			       ARRAY_SIZE(mux_pllmcp_clkm), 0,

			       clk_base + CLK_SOURCE_EMC,

			       29, 3, 0, NULL);

			       29, 3, 0, &emc_lock);



	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

				    &emc_lock);

	clks[TEGRA124_CLK_MC] = clk;



	/* cml0 */

	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,

drivers/clk/tegra/clk-tegra20.c

+7 −1
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ static struct cpu_clk_suspend_context { 
static void __iomem *clk_base;

static void __iomem *pmc_base;



static DEFINE_SPINLOCK(emc_lock);



#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,	\

			    _clk_num, _gate_flags, _clk_id)	\

	TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,	\
@@ -819,11 +821,15 @@ static void __init tegra20_periph_clk_init(void) 
			       ARRAY_SIZE(mux_pllmcp_clkm),

			       CLK_SET_RATE_NO_REPARENT,

			       clk_base + CLK_SOURCE_EMC,

			       30, 2, 0, NULL);

			       30, 2, 0, &emc_lock);

	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,

				    57, periph_clk_enb_refcnt);

	clks[TEGRA20_CLK_EMC] = clk;



	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

				    &emc_lock);

	clks[TEGRA20_CLK_MC] = clk;



	/* dsi */

	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,

				    48, periph_clk_enb_refcnt);

drivers/clk/tegra/clk-tegra30.c

+6 −1
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ static unsigned long input_freq; 


static DEFINE_SPINLOCK(cml_lock);

static DEFINE_SPINLOCK(pll_d_lock);

static DEFINE_SPINLOCK(emc_lock);



#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,	\

			    _clk_num, _gate_flags, _clk_id)	\
@@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void) 
			       ARRAY_SIZE(mux_pllmcp_clkm),

			       CLK_SET_RATE_NO_REPARENT,

			       clk_base + CLK_SOURCE_EMC,

			       30, 2, 0, NULL);

			       30, 2, 0, &emc_lock);

	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,

				    57, periph_clk_enb_refcnt);

	clks[TEGRA30_CLK_EMC] = clk;



	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

				    &emc_lock);

	clks[TEGRA30_CLK_MC] = clk;



	/* cml0 */

	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,

				0, 0, &cml_lock);