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Commit 4f1a1eb5 authored by Al Cooper's avatar Al Cooper Committed by Ralf Baechle
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MIPS: Kernel hangs occasionally during boot. 



The Kernel hangs occasionally during boot after "Calibrating delay loop..".
This is caused by the c0_compare_int_usable() routine in cevt-r4k.c
returning false which causes the system to disable the timer and hang later.
The false return happens because the routine is using a series of four calls
to irq_disable_hazard() as a delay while it waits for the timer changes to
propagate to the cp0 cause register. On newer MIPS cores, like the 74K, the
series of irq_disable_hazard() calls turn into ehb instructions and can take
as little as a few clock ticks for all 4 instructions. This is not enough of
a delay, so the routine thinks the timer is not working.  This fix uses up
to a max number of cycle counter ticks for the delay and uses
back_to_back_c0_hazard() instead of irq_disable_hazard() to handle the
hazard condition between cp0 writes and cp0 reads.

Signed-off-by: default avatarAl Cooper <alcooperx@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2911/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e63fb7a9

arch/mips/kernel/cevt-r4k.c

+19 −19
Original line number Diff line number Diff line
@@ -103,19 +103,10 @@ static int c0_compare_int_pending(void) 


/*

 * Compare interrupt can be routed and latched outside the core,

 * so a single execution hazard barrier may not be enough to give

 * it time to clear as seen in the Cause register.  4 time the

 * pipeline depth seems reasonably conservative, and empirically

 * works better in configurations with high CPU/bus clock ratios.

 * so wait up to worst case number of cycle counter ticks for timer interrupt

 * changes to propagate to the cause register.

 */



#define compare_change_hazard() \

	do { \

		irq_disable_hazard(); \

		irq_disable_hazard(); \

		irq_disable_hazard(); \

		irq_disable_hazard(); \

	} while (0)

#define COMPARE_INT_SEEN_TICKS 50



int c0_compare_int_usable(void)

{
@@ -126,8 +117,12 @@ int c0_compare_int_usable(void) 
	 * IP7 already pending?  Try to clear it by acking the timer.

	 */

	if (c0_compare_int_pending()) {

		write_c0_compare(read_c0_count());

		compare_change_hazard();

		cnt = read_c0_count();

		write_c0_compare(cnt);

		back_to_back_c0_hazard();

		while (read_c0_count() < (cnt  + COMPARE_INT_SEEN_TICKS))

			if (!c0_compare_int_pending())

				break;

		if (c0_compare_int_pending())

			return 0;

	}
@@ -136,7 +131,7 @@ int c0_compare_int_usable(void) 
		cnt = read_c0_count();

		cnt += delta;

		write_c0_compare(cnt);

		compare_change_hazard();

		back_to_back_c0_hazard();

		if ((int)(read_c0_count() - cnt) < 0)

		    break;

		/* increase delta if the timer was already expired */
@@ -145,12 +140,17 @@ int c0_compare_int_usable(void) 
	while ((int)(read_c0_count() - cnt) <= 0)

		;	/* Wait for expiry  */



	compare_change_hazard();

	while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))

		if (c0_compare_int_pending())

			break;

	if (!c0_compare_int_pending())

		return 0;



	write_c0_compare(read_c0_count());

	compare_change_hazard();

	cnt = read_c0_count();

	write_c0_compare(cnt);

	back_to_back_c0_hazard();

	while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))

		if (!c0_compare_int_pending())

			break;

	if (c0_compare_int_pending())

		return 0;