Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/ppc64-2.6 (4706df3d) · Commits · e / devices / android_kernel_samsung_universal8895

arch/ppc64/kernel/Makefile

+5 −3

Original line number	Original line	Diff line number	Diff line
	@@ -31,7 +31,7 @@ obj-$(CONFIG_PPC_MULTIPLATFORM) += nvram.o i8259.o prom_init.o prom.o

	obj-$(CONFIG_PPC_PSERIES) += pSeries_pci.o pSeries_lpar.o pSeries_hvCall.o \		obj-$(CONFIG_PPC_PSERIES) += pSeries_pci.o pSeries_lpar.o pSeries_hvCall.o \
	pSeries_nvram.o rtasd.o ras.o pSeries_reconfig.o \		pSeries_nvram.o rtasd.o ras.o pSeries_reconfig.o \
	pSeries_setup.o pSeries_iommu.o		pSeries_setup.o pSeries_iommu.o udbg_16550.o

	obj-$(CONFIG_PPC_BPA) += bpa_setup.o bpa_iommu.o bpa_nvram.o \		obj-$(CONFIG_PPC_BPA) += bpa_setup.o bpa_iommu.o bpa_nvram.o \
	bpa_iic.o spider-pic.o		bpa_iic.o spider-pic.o
	@@ -58,9 +58,11 @@ obj-$(CONFIG_XICS) += xics.o
	obj-$(CONFIG_MPIC) += mpic.o		obj-$(CONFIG_MPIC) += mpic.o

	obj-$(CONFIG_PPC_PMAC) += pmac_setup.o pmac_feature.o pmac_pci.o \		obj-$(CONFIG_PPC_PMAC) += pmac_setup.o pmac_feature.o pmac_pci.o \
	pmac_time.o pmac_nvram.o pmac_low_i2c.o		pmac_time.o pmac_nvram.o pmac_low_i2c.o \
			udbg_scc.o

	obj-$(CONFIG_PPC_MAPLE) += maple_setup.o maple_pci.o maple_time.o		obj-$(CONFIG_PPC_MAPLE) += maple_setup.o maple_pci.o maple_time.o \
			udbg_16550.o

	obj-$(CONFIG_U3_DART) += u3_iommu.o		obj-$(CONFIG_U3_DART) += u3_iommu.o

arch/ppc64/kernel/btext.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -7,7 +7,6 @@
	#include <linux/kernel.h>		#include <linux/kernel.h>
	#include <linux/string.h>		#include <linux/string.h>
	#include <linux/init.h>		#include <linux/init.h>
	#include <linux/version.h>

	#include <asm/sections.h>		#include <asm/sections.h>
	#include <asm/prom.h>		#include <asm/prom.h>

arch/ppc64/kernel/cputable.c

+77 −13

Original line number	Original line	Diff line number	Diff line
	@@ -19,6 +19,7 @@
	#include <linux/init.h>		#include <linux/init.h>
	#include <linux/module.h>		#include <linux/module.h>

			#include <asm/oprofile_impl.h>
	#include <asm/cputable.h>		#include <asm/cputable.h>

	struct cpu_spec* cur_cpu_spec = NULL;		struct cpu_spec* cur_cpu_spec = NULL;
	@@ -54,24 +55,32 @@ struct cpu_spec cpu_specs[] = {
	.pvr_value = 0x00400000,		.pvr_value = 0x00400000,
	.cpu_name = "POWER3 (630)",		.cpu_name = "POWER3 (630)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR,
	CPU_FTR_PMC8,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power3,		.cpu_setup = __setup_cpu_power3,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/power3",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* Power3+ */		{ /* Power3+ */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	.pvr_value = 0x00410000,		.pvr_value = 0x00410000,
	.cpu_name = "POWER3 (630+)",		.cpu_name = "POWER3 (630+)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR,
	CPU_FTR_PMC8,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power3,		.cpu_setup = __setup_cpu_power3,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/power3",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* Northstar */		{ /* Northstar */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -79,11 +88,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_name = "RS64-II (northstar)",		.cpu_name = "RS64-II (northstar)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
	CPU_FTR_PMC8 \| CPU_FTR_MMCRA \| CPU_FTR_CTRL,		CPU_FTR_MMCRA \| CPU_FTR_CTRL,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power3,		.cpu_setup = __setup_cpu_power3,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/rs64",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* Pulsar */		{ /* Pulsar */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -91,11 +105,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_name = "RS64-III (pulsar)",		.cpu_name = "RS64-III (pulsar)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
	CPU_FTR_PMC8 \| CPU_FTR_MMCRA \| CPU_FTR_CTRL,		CPU_FTR_MMCRA \| CPU_FTR_CTRL,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power3,		.cpu_setup = __setup_cpu_power3,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/rs64",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* I-star */		{ /* I-star */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -103,11 +122,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_name = "RS64-III (icestar)",		.cpu_name = "RS64-III (icestar)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
	CPU_FTR_PMC8 \| CPU_FTR_MMCRA \| CPU_FTR_CTRL,		CPU_FTR_MMCRA \| CPU_FTR_CTRL,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power3,		.cpu_setup = __setup_cpu_power3,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/rs64",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* S-star */		{ /* S-star */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -115,11 +139,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_name = "RS64-IV (sstar)",		.cpu_name = "RS64-IV (sstar)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
	CPU_FTR_PMC8 \| CPU_FTR_MMCRA \| CPU_FTR_CTRL,		CPU_FTR_MMCRA \| CPU_FTR_CTRL,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power3,		.cpu_setup = __setup_cpu_power3,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/rs64",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* Power4 */		{ /* Power4 */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -127,11 +156,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_name = "POWER4 (gp)",		.cpu_name = "POWER4 (gp)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,		CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power4,		.cpu_setup = __setup_cpu_power4,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/power4",
			.oprofile_model = &op_model_rs64,
			#endif
	},		},
	{ /* Power4+ */		{ /* Power4+ */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -139,11 +173,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_name = "POWER4+ (gq)",		.cpu_name = "POWER4+ (gq)",
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,		CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA,
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_power4,		.cpu_setup = __setup_cpu_power4,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/power4",
			.oprofile_model = &op_model_power4,
			#endif
	},		},
	{ /* PPC970 */		{ /* PPC970 */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -152,12 +191,17 @@ struct cpu_spec cpu_specs[] = {
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|		CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|
	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,		CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA,
	.cpu_user_features = COMMON_USER_PPC64 \|		.cpu_user_features = COMMON_USER_PPC64 \|
	PPC_FEATURE_HAS_ALTIVEC_COMP,		PPC_FEATURE_HAS_ALTIVEC_COMP,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_ppc970,		.cpu_setup = __setup_cpu_ppc970,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/970",
			.oprofile_model = &op_model_power4,
			#endif
	},		},
	{ /* PPC970FX */		{ /* PPC970FX */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -166,12 +210,17 @@ struct cpu_spec cpu_specs[] = {
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|		CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|
	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,		CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA,
	.cpu_user_features = COMMON_USER_PPC64 \|		.cpu_user_features = COMMON_USER_PPC64 \|
	PPC_FEATURE_HAS_ALTIVEC_COMP,		PPC_FEATURE_HAS_ALTIVEC_COMP,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 8,
	.cpu_setup = __setup_cpu_ppc970,		.cpu_setup = __setup_cpu_ppc970,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/970",
			.oprofile_model = &op_model_power4,
			#endif
	},		},
	{ /* PPC970MP */		{ /* PPC970MP */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -180,12 +229,16 @@ struct cpu_spec cpu_specs[] = {
	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|		.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|		CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|		CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|
	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,		CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA,
	.cpu_user_features = COMMON_USER_PPC64 \|		.cpu_user_features = COMMON_USER_PPC64 \|
	PPC_FEATURE_HAS_ALTIVEC_COMP,		PPC_FEATURE_HAS_ALTIVEC_COMP,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
	.cpu_setup = __setup_cpu_ppc970,		.cpu_setup = __setup_cpu_ppc970,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/970",
			.oprofile_model = &op_model_power4,
			#endif
	},		},
	{ /* Power5 */		{ /* Power5 */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -199,7 +252,12 @@ struct cpu_spec cpu_specs[] = {
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 6,
	.cpu_setup = __setup_cpu_power4,		.cpu_setup = __setup_cpu_power4,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/power5",
			.oprofile_model = &op_model_power4,
			#endif
	},		},
	{ /* Power5 */		{ /* Power5 */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -213,7 +271,12 @@ struct cpu_spec cpu_specs[] = {
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 6,
	.cpu_setup = __setup_cpu_power4,		.cpu_setup = __setup_cpu_power4,
			#ifdef CONFIG_OPROFILE
			.oprofile_cpu_type = "ppc64/power5",
			.oprofile_model = &op_model_power4,
			#endif
	},		},
	{ /* BE DD1.x */		{ /* BE DD1.x */
	.pvr_mask = 0xffff0000,		.pvr_mask = 0xffff0000,
	@@ -239,6 +302,7 @@ struct cpu_spec cpu_specs[] = {
	.cpu_user_features = COMMON_USER_PPC64,		.cpu_user_features = COMMON_USER_PPC64,
	.icache_bsize = 128,		.icache_bsize = 128,
	.dcache_bsize = 128,		.dcache_bsize = 128,
			.num_pmcs = 6,
	.cpu_setup = __setup_cpu_power4,		.cpu_setup = __setup_cpu_power4,
	}		}
	};		};

arch/ppc64/kernel/entry.S

+5 −6

Original line number	Original line	Diff line number	Diff line
	@@ -400,15 +400,14 @@ BEGIN_FTR_SECTION
	cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */		cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
	cror eq,4*cr1+eq,eq		cror eq,4*cr1+eq,eq
	beq 2f /* if yes, don't slbie it */		beq 2f /* if yes, don't slbie it */
	oris r0,r6,0x0800 /* set C (class) bit */

	/* Bolt in the new stack SLB entry */		/* Bolt in the new stack SLB entry */
	ld r7,KSP_VSID(r4) /* Get new stack's VSID */		ld r7,KSP_VSID(r4) /* Get new stack's VSID */
	oris r6,r6,(SLB_ESID_V)@h		oris r0,r6,(SLB_ESID_V)@h
	ori r6,r6,(SLB_NUM_BOLTED-1)@l		ori r0,r0,(SLB_NUM_BOLTED-1)@l
	slbie r0		slbie r6
	slbie r0 /* Workaround POWER5 < DD2.1 issue */		slbie r6 /* Workaround POWER5 < DD2.1 issue */
	slbmte r7,r6		slbmte r7,r0
	isync		isync

	2:		2:

arch/ppc64/kernel/head.S

+6 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1646,8 +1646,9 @@ _GLOBAL(__secondary_start)
	#else		#else
	/* set the ASR */		/* set the ASR */
	ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */		ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
			ld r3,0(r3)
	lwz r3,PLATFORM(r3) /* r3 = platform flags */		lwz r3,PLATFORM(r3) /* r3 = platform flags */
	cmpldi r3,PLATFORM_PSERIES_LPAR		andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
	bne 98f		bne 98f
	mfspr r3,PVR		mfspr r3,PVR
	srwi r3,r3,16		srwi r3,r3,16
	@@ -1809,8 +1810,9 @@ _STATIC(start_here_multiplatform)
	ld r3,PACASTABREAL(r13)		ld r3,PACASTABREAL(r13)
	ori r4,r3,1 /* turn on valid bit */		ori r4,r3,1 /* turn on valid bit */
	ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */		ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
			ld r3,0(r3)
	lwz r3,PLATFORM(r3) /* r3 = platform flags */		lwz r3,PLATFORM(r3) /* r3 = platform flags */
	cmpldi r3,PLATFORM_PSERIES_LPAR		andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
	bne 98f		bne 98f
	mfspr r3,PVR		mfspr r3,PVR
	srwi r3,r3,16		srwi r3,r3,16
	@@ -1828,9 +1830,10 @@ _STATIC(start_here_multiplatform)
	99:		99:
	/* Set SDR1 (hash table pointer) */		/* Set SDR1 (hash table pointer) */
	ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */		ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
			ld r3,0(r3)
	lwz r3,PLATFORM(r3) /* r3 = platform flags */		lwz r3,PLATFORM(r3) /* r3 = platform flags */
	/* Test if bit 0 is set (LPAR bit) */		/* Test if bit 0 is set (LPAR bit) */
	andi. r3,r3,0x1		andi. r3,r3,PLATFORM_LPAR
	bne 98f		bne 98f
	LOADADDR(r6,_SDR1) /* Only if NOT LPAR */		LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
	sub r6,r6,r26		sub r6,r6,r26