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Commit 46fda15c authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock 



The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.

Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarJaswinder Singh <jaswinder.singh@linaro.org>
[kgene.kim@samsung.com: changed the name of clk for consensus]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 4922972e

arch/arm/mach-exynos/clock-exynos4.c

+39 −10
Original line number Original line Diff line number Diff line
@@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { 
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },

};

};





static struct clksrc_clk exynos4_clk_mdout_spi0 = {

	.clk	= {

		.name		= "mdout_spi",

		.devname	= "exynos4210-spi.0",

	},

	.sources = &exynos4_clkset_group,

	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },

};



static struct clksrc_clk exynos4_clk_mdout_spi1 = {

	.clk	= {

		.name		= "mdout_spi",

		.devname	= "exynos4210-spi.1",

	},

	.sources = &exynos4_clkset_group,

	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },

};



static struct clksrc_clk exynos4_clk_mdout_spi2 = {

	.clk	= {

		.name		= "mdout_spi",

		.devname	= "exynos4210-spi.2",

	},

	.sources = &exynos4_clkset_group,

	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },

};



static struct clksrc_clk exynos4_clk_sclk_spi0 = {

static struct clksrc_clk exynos4_clk_sclk_spi0 = {

	.clk	= {

	.clk	= {

		.name		= "sclk_spi",

		.name		= "sclk_spi",

		.devname	= "exynos4210-spi.0",

		.devname	= "exynos4210-spi.0",

		.parent		= &exynos4_clk_mdout_spi0.clk,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit	= (1 << 16),

		.ctrlbit	= (1 << 16),

	},

	},

	.sources = &exynos4_clkset_group,

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },

	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },

};

};





static struct clksrc_clk exynos4_clk_sclk_spi1 = {

static struct clksrc_clk exynos4_clk_sclk_spi1 = {

	.clk	= {

	.clk	= {

		.name		= "sclk_spi",

		.name		= "sclk_spi",

		.devname	= "exynos4210-spi.1",

		.devname	= "exynos4210-spi.1",

		.parent		= &exynos4_clk_mdout_spi1.clk,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit	= (1 << 20),

		.ctrlbit	= (1 << 20),

	},

	},

	.sources = &exynos4_clkset_group,

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },

	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },

};

};





static struct clksrc_clk exynos4_clk_sclk_spi2 = {

static struct clksrc_clk exynos4_clk_sclk_spi2 = {

	.clk	= {

	.clk	= {

		.name		= "sclk_spi",

		.name		= "sclk_spi",

		.devname	= "exynos4210-spi.2",

		.devname	= "exynos4210-spi.2",

		.parent		= &exynos4_clk_mdout_spi2.clk,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.enable		= exynos4_clksrc_mask_peril1_ctrl,

		.ctrlbit	= (1 << 24),

		.ctrlbit	= (1 << 24),

	},

	},

	.sources = &exynos4_clkset_group,

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },

	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },

	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },

};

};





/* Clock initialization code */

/* Clock initialization code */
@@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { 
	&exynos4_clk_sclk_spi0,

	&exynos4_clk_sclk_spi0,

	&exynos4_clk_sclk_spi1,

	&exynos4_clk_sclk_spi1,

	&exynos4_clk_sclk_spi2,

	&exynos4_clk_sclk_spi2,



	&exynos4_clk_mdout_spi0,

	&exynos4_clk_mdout_spi1,

	&exynos4_clk_mdout_spi2,

};

};





static struct clk_lookup exynos4_clk_lookup[] = {

static struct clk_lookup exynos4_clk_lookup[] = {