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Commit 454fc95e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: fix the build on big endian 



Some leftover copy and pastes from radeon that never
got updated.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reported-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 675da0dd

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+2 −1
Original line number Diff line number Diff line
@@ -411,7 +411,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 
		rb_bufsz = order_base_2(ring->ring_size / 4);

		rb_cntl = rb_bufsz << 1;

#ifdef __BIG_ENDIAN

		rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;

		rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |

			SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;

#endif

		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+3 −2
Original line number Diff line number Diff line
@@ -2881,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 
	rb_bufsz = order_base_2(ring->ring_size / 8);

	tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

	tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;

#endif

	WREG32(mmCP_RB0_CNTL, tmp);
@@ -3400,7 +3400,8 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 
		mqd->queue_state.cp_hqd_pq_control |=

			(order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);

#ifdef __BIG_ENDIAN

		mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;

		mqd->queue_state.cp_hqd_pq_control |=

			2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;

#endif

		mqd->queue_state.cp_hqd_pq_control &=

			~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |