Commit 42ff6572 authored Dec 22, 2011 by Eric Anholt Committed by Keith Packard Jan 03, 2012

drm/i915: Work around gen7 BLT ring synchronization issues.



Previous to this commit, testing easily reproduced a failure where the
seqno would apparently arrive after the IRQ associated with it, with test programs as simple as:

for (;;) {
    glCopyPixels(0, 0, 1, 1);
    glFinish();
}

Various workarounds we've seen for previous generations didn't work to
fix this issue, so until new information comes in, replace the IRQ
waits on the BLT ring with polling.

Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Keith Packard <keithp@keithp.com>

parent 7ea29b13

drivers/gpu/drm/i915/intel_ringbuffer.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -791,6 +791,17 @@ ring_add_request(struct intel_ring_buffer *ring,
		return 0;
		}

		static bool
		gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
		{
		/* The BLT ring on IVB appears to have broken synchronization
		* between the seqno write and the interrupt, so that the
		* interrupt appears first. Returning false here makes
		* i915_wait_request() do a polling loop, instead.
		*/
		return false;
		}

		static bool
		gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
		{
		@@ -1557,5 +1568,8 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)

		*ring = gen6_blt_ring;

		if (IS_GEN7(dev))
		ring->irq_get = gen7_blt_ring_get_irq;

		return intel_init_ring_buffer(dev, ring);
		}