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Commit 42b5f406 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Gregory CLEMENT
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clk: mvebu: extend common code to allow an optional refclk 



The Armada 39x, contrary to its predecessor, has a configurable
reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
previous SoCs, it was fixed to 25 Mhz and described directly as such
in the Device Tree.

For Armada 39x, we need to read certain registers to know whether the
frequency is 25 or 40 Mhz. Therefore, this commit extends the common
mvebu clock code to allow the SoC-specific code to say it wants to
register a reference clock, by giving a non-NULL ->get_refclk_freq()
function pointer in its coreclk_soc_desc structure.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 9baf9688

drivers/clk/mvebu/common.c

+17 −0
Original line number Original line Diff line number Diff line
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np, 




	/* Allocate struct for TCLK, cpu clk, and core ratio clocks */

	/* Allocate struct for TCLK, cpu clk, and core ratio clocks */

	clk_data.clk_num = 2 + desc->num_ratios;

	clk_data.clk_num = 2 + desc->num_ratios;



	/* One more clock for the optional refclk */

	if (desc->get_refclk_freq)

		clk_data.clk_num += 1;



	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),

	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),

				GFP_KERNEL);

				GFP_KERNEL);

	if (WARN_ON(!clk_data.clks)) {

	if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np, 
		WARN_ON(IS_ERR(clk_data.clks[2+n]));

		WARN_ON(IS_ERR(clk_data.clks[2+n]));

	};

	};





	/* Register optional refclk */

	if (desc->get_refclk_freq) {

		const char *name = "refclk";

		of_property_read_string_index(np, "clock-output-names",

					      2 + desc->num_ratios, &name);

		rate = desc->get_refclk_freq(base);

		clk_data.clks[2 + desc->num_ratios] =

			clk_register_fixed_rate(NULL, name, NULL,

						CLK_IS_ROOT, rate);

		WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));

	}



	/* SAR register isn't needed anymore */

	/* SAR register isn't needed anymore */

	iounmap(base);

	iounmap(base);

drivers/clk/mvebu/common.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -30,6 +30,7 @@ struct coreclk_soc_desc { 
	u32 (*get_tclk_freq)(void __iomem *sar);

	u32 (*get_tclk_freq)(void __iomem *sar);

	u32 (*get_cpu_freq)(void __iomem *sar);

	u32 (*get_cpu_freq)(void __iomem *sar);

	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);

	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);

	u32 (*get_refclk_freq)(void __iomem *sar);

	bool (*is_sscg_enabled)(void __iomem *sar);

	bool (*is_sscg_enabled)(void __iomem *sar);

	u32 (*fix_sscg_deviation)(u32 system_clk);

	u32 (*fix_sscg_deviation)(u32 system_clk);

	const struct coreclk_ratio *ratios;

	const struct coreclk_ratio *ratios;