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Commit 3c321bce authored by Vivek Goyal's avatar Vivek Goyal Committed by Andi Kleen
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[PATCH] x86-64: Add EFER to the register set saved by save_processor_state



EFER varies like %cr4 depending on the cpu capabilities, and which cpu
capabilities we want to make use of.  So save/restore it make certain
we have the same EFER value when we are done.

Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
Signed-off-by: default avatarVivek Goyal <vgoyal@in.ibm.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent 30f47289
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+2 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ void __save_processor_state(struct saved_context *ctxt)
	asm volatile ("str %0"  : "=m" (ctxt->tr));

	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
	/* EFER should be constant for kernel version, no need to handle it. */
	/*
	 * segment registers
	 */
@@ -50,6 +49,7 @@ void __save_processor_state(struct saved_context *ctxt)
	/*
	 * control registers 
	 */
	rdmsrl(MSR_EFER, ctxt->efer);
	asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
	asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
	asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
@@ -75,6 +75,7 @@ void __restore_processor_state(struct saved_context *ctxt)
	/*
	 * control registers
	 */
	wrmsrl(MSR_EFER, ctxt->efer);
	asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
	asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
	asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ struct saved_context {
  	u16 ds, es, fs, gs, ss;
	unsigned long gs_base, gs_kernel_base, fs_base;
	unsigned long cr0, cr2, cr3, cr4, cr8;
	unsigned long efer;
	u16 gdt_pad;
	u16 gdt_limit;
	unsigned long gdt_base;