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Commit 37d5993c authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: Fix WM8996 24.576MHz clock operation 



Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
parent 974edd30

sound/soc/codecs/wm8996.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1968,6 +1968,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai, 
		break;

		break;

	case 24576000:

	case 24576000:

		ratediv = WM8996_SYSCLK_DIV;

		ratediv = WM8996_SYSCLK_DIV;

		wm8996->sysclk /= 2;

	case 12288000:

	case 12288000:

		snd_soc_update_bits(codec, WM8996_AIF_RATE,

		snd_soc_update_bits(codec, WM8996_AIF_RATE,

				    WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);

				    WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);