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Commit 37b25fff authored by Jason Cooper's avatar Jason Cooper
Browse files

Merge branch 'irqchip/stacked-tegra' into irqchip/core

parents 78223354 1eec5821

Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt

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NVIDIA Legacy Interrupt Controller



All Tegra SoCs contain a legacy interrupt controller that routes

interrupts to the GIC, and also serves as a wakeup source. It is also

referred to as "ictlr", hence the name of the binding.



The HW block exposes a number of interrupt controllers, each

implementing a set of 32 interrupts.



Required properties:



- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on

  subsequent SoCs remained backwards-compatible with Tegra30, so on

  Tegra generations later than Tegra30 the compatible value should

  include "nvidia,tegra30-ictlr".	

- reg : Specifies base physical address and size of the registers.

  Each controller must be described separately (Tegra20 has 4 of them,

  whereas Tegra30 and later have 5"  

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value must be 3.

- interrupt-parent : a phandle to the GIC these interrupts are routed

  to.



Notes:



- Because this HW ultimately routes interrupts to the GIC, the

  interrupt specifier must be that of the GIC.

- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs

  are explicitly forbidden.



Example:



	ictlr: interrupt-controller@60004000 {

		compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";

		reg = <0x60004000 64>,

		      <0x60004100 64>,

		      <0x60004200 64>,

		      <0x60004300 64>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;

	};

arch/arm/boot/dts/tegra114.dtsi

+15 −1
Original line number Original line Diff line number Diff line
@@ -8,7 +8,7 @@ 




/ {

/ {

	compatible = "nvidia,tegra114";

	compatible = "nvidia,tegra114";

	interrupt-parent = <&gic>;

	interrupt-parent = <&lic>;





	host1x@50000000 {

	host1x@50000000 {

		compatible = "nvidia,tegra114-host1x", "simple-bus";

		compatible = "nvidia,tegra114-host1x", "simple-bus";
@@ -134,6 +134,19 @@ 
		      <0x50046000 0x2000>;

		      <0x50046000 0x2000>;

		interrupts = <GIC_PPI 9

		interrupts = <GIC_PPI 9

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		interrupt-parent = <&gic>;

	};



	lic: interrupt-controller@60004000 {

		compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";

		reg = <0x60004000 0x100>,

		      <0x60004100 0x50>,

		      <0x60004200 0x50>,

		      <0x60004300 0x50>,

		      <0x60004400 0x50>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&gic>;

	};

	};





	timer@60005000 {

	timer@60005000 {
@@ -766,5 +779,6 @@ 
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			<GIC_PPI 10

			<GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

	};

	};

};
 
};

arch/arm/boot/dts/tegra124.dtsi

+15 −1
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@@ -10,7 +10,7 @@ 




/ {

/ {

	compatible = "nvidia,tegra124";

	compatible = "nvidia,tegra124";

	interrupt-parent = <&gic>;

	interrupt-parent = <&lic>;

	#address-cells = <2>;

	#address-cells = <2>;

	#size-cells = <2>;

	#size-cells = <2>;
@@ -173,6 +173,7 @@ 
		      <0x0 0x50046000 0x0 0x2000>;

		      <0x0 0x50046000 0x0 0x2000>;

		interrupts = <GIC_PPI 9

		interrupts = <GIC_PPI 9

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		interrupt-parent = <&gic>;

	};

	};





	gpu@0,57000000 {

	gpu@0,57000000 {
@@ -190,6 +191,18 @@ 
		status = "disabled";

		status = "disabled";

	};

	};





	lic: interrupt-controller@60004000 {

		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";

		reg = <0x0 0x60004000 0x0 0x100>,

		      <0x0 0x60004100 0x0 0x100>,

		      <0x0 0x60004200 0x0 0x100>,

		      <0x0 0x60004300 0x0 0x100>,

		      <0x0 0x60004400 0x0 0x100>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&gic>;

	};



	timer@0,60005000 {

	timer@0,60005000 {

		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";

		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";

		reg = <0x0 0x60005000 0x0 0x400>;

		reg = <0x0 0x60005000 0x0 0x400>;
@@ -955,5 +968,6 @@ 
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

			     <GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

	};

	};

};
 
};

arch/arm/boot/dts/tegra20.dtsi

+14 −1
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@@ -7,7 +7,7 @@ 




/ {

/ {

	compatible = "nvidia,tegra20";

	compatible = "nvidia,tegra20";

	interrupt-parent = <&intc>;

	interrupt-parent = <&lic>;





	host1x@50000000 {

	host1x@50000000 {

		compatible = "nvidia,tegra20-host1x", "simple-bus";

		compatible = "nvidia,tegra20-host1x", "simple-bus";
@@ -142,6 +142,7 @@ 




	timer@50040600 {

	timer@50040600 {

		compatible = "arm,cortex-a9-twd-timer";

		compatible = "arm,cortex-a9-twd-timer";

		interrupt-parent = <&intc>;

		reg = <0x50040600 0x20>;

		reg = <0x50040600 0x20>;

		interrupts = <GIC_PPI 13

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -154,6 +155,7 @@ 
		       0x50040100 0x0100>;

		       0x50040100 0x0100>;

		interrupt-controller;

		interrupt-controller;

		#interrupt-cells = <3>;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;

	};

	};





	cache-controller@50043000 {

	cache-controller@50043000 {
@@ -165,6 +167,17 @@ 
		cache-level = <2>;

		cache-level = <2>;

	};

	};





	lic: interrupt-controller@60004000 {

		compatible = "nvidia,tegra20-ictlr";

		reg = <0x60004000 0x100>,

		      <0x60004100 0x50>,

		      <0x60004200 0x50>,

		      <0x60004300 0x50>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;

	};



	timer@60005000 {

	timer@60005000 {

		compatible = "nvidia,tegra20-timer";

		compatible = "nvidia,tegra20-timer";

		reg = <0x60005000 0x60>;

		reg = <0x60005000 0x60>;

arch/arm/boot/dts/tegra30.dtsi

+15 −1
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@@ -8,7 +8,7 @@ 




/ {

/ {

	compatible = "nvidia,tegra30";

	compatible = "nvidia,tegra30";

	interrupt-parent = <&intc>;

	interrupt-parent = <&lic>;





	pcie-controller@00003000 {

	pcie-controller@00003000 {

		compatible = "nvidia,tegra30-pcie";

		compatible = "nvidia,tegra30-pcie";
@@ -228,6 +228,7 @@ 
	timer@50040600 {

	timer@50040600 {

		compatible = "arm,cortex-a9-twd-timer";

		compatible = "arm,cortex-a9-twd-timer";

		reg = <0x50040600 0x20>;

		reg = <0x50040600 0x20>;

		interrupt-parent = <&intc>;

		interrupts = <GIC_PPI 13

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		clocks = <&tegra_car TEGRA30_CLK_TWD>;

		clocks = <&tegra_car TEGRA30_CLK_TWD>;
@@ -239,6 +240,7 @@ 
		       0x50040100 0x0100>;

		       0x50040100 0x0100>;

		interrupt-controller;

		interrupt-controller;

		#interrupt-cells = <3>;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;

	};

	};





	cache-controller@50043000 {

	cache-controller@50043000 {
@@ -250,6 +252,18 @@ 
		cache-level = <2>;

		cache-level = <2>;

	};

	};





	lic: interrupt-controller@60004000 {

		compatible = "nvidia,tegra30-ictlr";

		reg = <0x60004000 0x100>,

		      <0x60004100 0x50>,

		      <0x60004200 0x50>,

		      <0x60004300 0x50>,

		      <0x60004400 0x50>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;

	};



	timer@60005000 {

	timer@60005000 {

		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";

		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";

		reg = <0x60005000 0x400>;

		reg = <0x60005000 0x400>;