Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3518dd14 authored by Andreas Herrmann's avatar Andreas Herrmann Committed by H. Peter Anvin
Browse files

x86, cacheinfo: Fix dependency of AMD L3 CID 



L3 cache index disable code uses PCI accesses to AMD northbridge functions.
Currently the code is #ifdef CONFIG_CPU_SUP_AMD.
But it should be #if (defined(CONFIG_CPU_SUP_AMD) && defined(CONFIG_PCI))
which in the end is a dependency to K8_NB.

Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100917160744.GF4958@loge.amd.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 509344b8

arch/x86/kernel/cpu/intel_cacheinfo.c

+4 −4
Original line number Diff line number Diff line
@@ -306,7 +306,7 @@ struct _cache_attr { 
	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);

};



#ifdef CONFIG_CPU_SUP_AMD

#ifdef CONFIG_K8_NB



/*

 * L3 cache descriptors
@@ -556,12 +556,12 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, 
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,

		show_cache_disable_1, store_cache_disable_1);



#else	/* CONFIG_CPU_SUP_AMD */

#else	/* CONFIG_K8_NB */

static void __cpuinit

amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)

{

};

#endif /* CONFIG_CPU_SUP_AMD */

#endif /* CONFIG_K8_NB */



static int

__cpuinit cpuid4_cache_lookup_regs(int index,
@@ -1000,7 +1000,7 @@ static struct attribute *default_attrs[] = { 


static struct attribute *default_l3_attrs[] = {

	DEFAULT_SYSFS_CACHE_ATTRS,

#ifdef CONFIG_CPU_SUP_AMD

#ifdef CONFIG_K8_NB

	&cache_disable_0.attr,

	&cache_disable_1.attr,

#endif