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Commit 338a95a9 authored by Alex Deucher's avatar Alex Deucher
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drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag 



Some asic revisions need to disable PG when UVD is active.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 62fa44bf

drivers/gpu/drm/radeon/sumo_dpm.c

+3 −1
Original line number Diff line number Diff line
@@ -824,6 +824,8 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev, 
	radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);



	if (pi->enable_gfx_power_gating) {

		if (!pi->disable_gfx_power_gating_in_uvd ||

		    !r600_is_uvd_state(new_rps->class, new_rps->class2))

			sumo_gfx_powergating_enable(rdev, true);

	}

}