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Commit 3070033a authored by Steven J. Hill's avatar Steven J. Hill
Browse files

MIPS: Add core files for MIPS SEAD-3 development platform. 

More information about the SEAD-3 platform can be found at
<http://www.mips.com/products/development-kits/mips-sead-3/

>
on MTI's site. Currently, the M14K family of cores is what
the SEAD-3 is utilised with.

Signed-off-by: default avatarDouglas Leung <douglas@mips.com>
Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
parent 006a851b

arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h

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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2003, 2004 Chris Dearman

 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)

 */

#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H

#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H





/*

 * CPU feature overrides for MIPS boards

 */

#ifdef CONFIG_CPU_MIPS32

#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_4k_cache	1

/* #define cpu_has_fpu		? */

/* #define cpu_has_32fpr	? */

#define cpu_has_counter		1

/* #define cpu_has_watch	? */

#define cpu_has_divec		1

#define cpu_has_vce		0

/* #define cpu_has_cache_cdex_p	? */

/* #define cpu_has_cache_cdex_s	? */

/* #define cpu_has_prefetch	? */

#define cpu_has_mcheck		1

/* #define cpu_has_ejtag	? */

#ifdef CONFIG_CPU_HAS_LLSC

#define cpu_has_llsc		1

#else

#define cpu_has_llsc		0

#endif

/* #define cpu_has_vtag_icache	? */

/* #define cpu_has_dc_aliases	? */

/* #define cpu_has_ic_fills_f_dc ? */

#define cpu_has_nofpuex		0

/* #define cpu_has_64bits	? */

/* #define cpu_has_64bit_zero_reg ? */

/* #define cpu_has_inclusive_pcaches ? */

#define cpu_icache_snoops_remote_store 1

#endif



#ifdef CONFIG_CPU_MIPS64

#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_4k_cache	1

/* #define cpu_has_fpu		? */

/* #define cpu_has_32fpr	? */

#define cpu_has_counter		1

/* #define cpu_has_watch	? */

#define cpu_has_divec		1

#define cpu_has_vce		0

/* #define cpu_has_cache_cdex_p	? */

/* #define cpu_has_cache_cdex_s	? */

/* #define cpu_has_prefetch	? */

#define cpu_has_mcheck		1

/* #define cpu_has_ejtag	? */

#define cpu_has_llsc		1

/* #define cpu_has_vtag_icache	? */

/* #define cpu_has_dc_aliases	? */

/* #define cpu_has_ic_fills_f_dc ? */

#define cpu_has_nofpuex		0

/* #define cpu_has_64bits	? */

/* #define cpu_has_64bit_zero_reg ? */

/* #define cpu_has_inclusive_pcaches ? */

#define cpu_icache_snoops_remote_store 1

#endif



#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-sead3/irq.h

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#ifndef __ASM_MACH_MIPS_IRQ_H

#define __ASM_MACH_MIPS_IRQ_H



#define NR_IRQS	256





#include_next <irq.h>



#endif /* __ASM_MACH_MIPS_IRQ_H */

arch/mips/include/asm/mach-sead3/kernel-entry-init.h

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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Chris Dearman (chris@mips.com)

 * Copyright (C) 2007 Mips Technologies, Inc.

 */

#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H

#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H



	.macro	kernel_entry_setup

#ifdef CONFIG_MIPS_MT_SMTC

	mfc0	t0, CP0_CONFIG

	bgez	t0, 9f

	mfc0	t0, CP0_CONFIG, 1

	bgez	t0, 9f

	mfc0	t0, CP0_CONFIG, 2

	bgez	t0, 9f

	mfc0	t0, CP0_CONFIG, 3

	and	t0, 1<<2

	bnez	t0, 0f

9 :

	/* Assume we came from YAMON... */

	PTR_LA	v0, 0x9fc00534	/* YAMON print */

	lw	v0, (v0)

	move	a0, zero

	PTR_LA	a1, nonmt_processor

	jal	v0



	PTR_LA	v0, 0x9fc00520	/* YAMON exit */

	lw	v0, (v0)

	li	a0, 1

	jal	v0



1 :	b	1b



	__INITDATA

nonmt_processor :

	.asciz	"SMTC kernel requires the MT ASE to run\n"

	__FINIT

0 :

#endif

	.endm



/*

 * Do SMP slave processor setup necessary before we can safely execute C code.

 */

	.macro	smp_slave_setup

	.endm



#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */

arch/mips/include/asm/mach-sead3/war.h

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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>

 */

#ifndef __ASM_MIPS_MACH_MIPS_WAR_H

#define __ASM_MIPS_MACH_MIPS_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	1

#define MIPS_CACHE_SYNC_WAR		1

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define RM9000_CDEX_SMP_WAR		0

#define ICACHE_REFILLS_WORKAROUND_WAR	1

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

arch/mips/include/asm/mips-boards/sead3int.h

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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.

 *      Douglas Leung <douglas@mips.com>

 *      Steven J. Hill <sjhill@mips.com>

 */

#ifndef _MIPS_SEAD3INT_H

#define _MIPS_SEAD3INT_H



/* SEAD-3 GIC address space definitions. */

#define GIC_BASE_ADDR		0x1b1c0000

#define GIC_ADDRSPACE_SZ	(128 * 1024)



#define MIPS_GIC_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 0)



#endif /* !(_MIPS_SEAD3INT_H) */